Diffusion break forming after source/drain forming and related IC structure

Patent metadata

Field	Value
Publication number	US-9917103-B1
Application number	US-201715397978-A
Country	US
Kind code	B1
Filing date	Jan 4, 2017
Priority date	Jan 4, 2017
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Methods of forming a diffusion break are disclosed. The method includes forming a diffusion break after source/drain formation, by removing a gate stack of the dummy gate to a buried insulator of an SOI substrate, creating a first opening; and filling the first opening with a dielectric to form the diffusion break. An IC structure includes the diffusion break in contact with an upper surface of the buried insulator. In an optional embodiment, the method may also include simultaneously forming an isolation in an active gate to an STI in the SOI substrate.

First claim

What is claimed is:

1. A method of forming a diffusion break, the method comprising:
providing a structure including:
a semiconductor-on-insulator (SOI) substrate having a plurality of active gates and a dummy gate between a selected pair of active gates of the plurality of active gates,
a raised source/drain region between each of the selected pair of active gates and the dummy gate; and
a shallow trench isolation (STI) gate cut region including a STI in the SOI substrate below a portion of a selected active gate of the plurality of active gates;

forming the diffusion break by:
removing a gate stack of the dummy gate to a buried insulator of the SOI substrate, creating a first opening; and
filling the first opening with a dielectric to form the diffusion break, the diffusion break in contact with an upper surface of the buried insulator; and

forming, simultaneously with the forming the diffusion break, an isolation in the selected active gate of the plurality of active gates, the isolation separating the selected active gate into two isolated active gate portions, and wherein the isolation is positioned over the STI.

2. The method of claim 1 , wherein forming the diffusion break and the isolation in the selected active gate includes:
forming a silicide using a silicide mask covering the dummy gate and the STI gate cut region;
depositing a contact etch stop layer;
forming a dielectric layer that exposes the contact etch stop layer selectively over the dummy gate and over the STI gate cut region;
etching the contact etch stop layer to expose the gate stack of the dummy gate and expose the selected active gate in the STI gate cut region,
wherein removing the gate stack of the dummy gate also includes removing the selected active gate to the STI, creating a second opening, and
wherein filling the first opening with the dielectric includes filling the second opening with the dielectric to form the isolation in the selected active gate, the isolation being in contact with the STI.

3. The method of claim 2 , wherein, prior to etching the etch stop layer, forming a spacer in an opening in the dielectric layer in the STI gate cut region.

4. The method of claim 1 , further comprising, prior to removing the dummy gate:
forming a silicide using a silicide mask covering the dummy gate;
depositing an contact etch stop layer;
forming a dielectric layer, leaving the contact etch stop layer over the gate stack of the dummy gate exposed; and
etching the contact etch stop layer to expose the gate stack of the dummy gate.

5. The method of claim 4 , wherein the silicide mask also covers a polysilicon resistor on the SOI substrate.

6. The method of claim 1 , further comprising forming a spacer within the first opening prior to the filling with the dielectric.

7. The method of claim 1 , wherein providing the structure further includes imparting a compressive strain in an SOI layer of the SOI substrate used as a channel region for the plurality of active gates.

8. A method comprising:
providing a fully depleted semiconductor-on-insulator (FDSOI) substrate including:
a plurality of gates in a semiconductor-on-insulator (SOI) layer of the FDSOI substrate, the plurality of gates including: a plurality of active gates including a selected pair of active gates, each active gate of the selected pair of active gates including a channel region having a compressive strain therein, and a dummy gate between the selected pair of active gates,
a raised source/drain region adjacent each active gate and between each active gate of the selected pair of active gates and the dummy gate, and
a shallow trench isolation (STI) gate cut region including an STI in the FDSOI substrate below a portion of a selected active gate of the plurality of active gates;

forming a silicide using a silicide mask covering the dummy gate and the STI gate cut region;
depositing an contact etch stop layer;
forming a dielectric layer that exposes the contact etch stop layer selectively over a gate stack of the dummy gate and the contact etch stop layer over the selected active gate over the STI gate cut region;
etching the contact etch stop layer to expose the gate stack of the dummy gate and expose the selected active gate in the STI gate cut region;
etching to: remove the gate stack of the dummy gate to a buried insulator of the FDSOI substrate, creating a first opening, and remove a gate stack of the selected active gate to the STI, creating a second opening, and
filling the first opening and the second opening with a dielectric to form a diffusion break to the buried insulator layer in the first opening and an isolation in the selected active gate to the STI in the second opening.

9. The method of claim 8 , wherein the silicide mask also covers a polysilicon resistor.

10. The method of claim 8 , further comprising forming a spacer within the first opening prior to the filling with the dielectric.

11. The method of claim 8 , wherein, prior to the etching the etch stop layer, forming a spacer in an opening in the dielectric layer in the STI gate cut region.

12. An integrated circuit (IC) structure, comprising:
a semiconductor-on-insulator (SOI) substrate including an SOI layer over a buried insulator;
a pair of first active gates formed with the SOI layer;
a dummy gate formed with the SOI layer between the pair of first active gates;
a diffusion break positioned below the dummy gate, the diffusion break extending to an upper surface of the buried insulator; and
a second active gate distinct from the pair of first active gates, the second active gate including an isolation separating the second active gate into two isolated active gate portions, the isolation extending to a shallow trench isolation in the SOI substrate.

13. The IC structure of claim 12 , wherein the diffusion break is self-aligned with the dummy gate thereover.

14. The IC structure of claim 12 , wherein the SOI layer includes a compressive stress or a tensile stress.

15. The IC structure of claim 12 , further comprising a spacer between the isolation and each of the two isolated active gate portions.

16. The IC structure of claim 12 , wherein the SOI substrate includes a fully depleted semiconductor-on-insulator (FDSOI) substrate, and the pair of active gates each form a p-type field effect transistor.

17. The IC structure of claim 12 , wherein the pair of active gates each form an n-type field effect transistor.

18. The IC structure of claim 12 , further comprising a raised source/drain region between each active gate and the dummy gate, the raised source/drain region being facet free adjacent the diffusion break.

Assignees

• Globalfoundries Inc

Inventors

• Mulfinger George R
• Wallner Jin Z

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title