Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE)

Patent metadata

Field	Value
Publication number	US-10103172-B2
Application number	US-201715613712-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Sep 22, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

First claim

We claim:

1. A method of fabricating a Fin Field Effect Transistor (FinFet) structure using Local Layout Effects (LLE), the method comprising:
removing one or more fingers of an active P-type FinFet (PFET) gate of some PFET gates from a standard FinFet cell;
introducing a Half-Double Diffusion Break (Half-DDB) on an N-type FinFET (NFET) side of a cell boundary using a cut-poly layer to isolate the some PFET gates and some NFET gates; and
converting the removed one or more fingers of the active PFET gate to at least two floating PFET gates by shorting a drain terminal and a source terminal of the active PFET gate to a common net.

2. The method of claim 1 , wherein converting the removed one or more fingers of the active PFET gate includes:
converting the removed one or more PFET fingers of the active PFET gate to at least two floating PFET gates by shorting the drain terminal and the source terminal of the active PFET gate to one of a common internal net and a common power net.

3. The method of claim 1 , further comprising:
removing one or more fins from the NFET side of the cell boundary.

4. The method of claim 1 , further comprising:
removing one or more PFET fins along with one or more PFET fingers; and
converting the removed one or more PFET fingers of the active PFET gate to at least two floating PFET gates by shorting the drain terminal and the source terminal of the active PFET gate to one of a common power net and a common internal net.

5. The method of claim 1 , further comprising:
removing one or more NFET fins from the NFET side of the cell boundary; and
retaining the some of the PFET gates in active state.

6. The method of claim 1 , further comprising:
removing one or more PFET fins while retaining some of the PFET gates in active state.

7. The method of claim 1 , further comprising:
converting at least one of the some PFET gates cut from the some NFET gates to a floating gate, where the drain terminal and source terminal of the floating gate is connected to one of a common power net and common internal net,
where another at least one of the some PFET gates is converted to an inactive gate using a Single Diffusion Break on the PFET gate cut from the NFET gate.

8. The method of claim 7 , wherein, when viewed from a plan view, a position of the at least one floating gate is one of to a left of the Single Diffusion Break and to a right of the Single Diffusion Break.

9. The method of claim 1 , further comprising:
converting at least one DDB of a standard FinFet cell to a half-DDB on the NFET side inside the cell boundary using a cut poly layer to isolate the PFET gates and the NFET gates.

10. The method of claim 1 , further comprising:
introducing a hybrid DDB structure on the standard FinFet cell; and
removing one or more NFET fins belonging to one or more inputs.

11. The method of claim 1 , further comprising:
inserting the Half-DDB on an N-type FinFet (NFET) side of the cell boundary using the cut-poly layer to isolate the PFET and NFET gates; and
removing one or more NFET fins belonging to an input directly connected to an outside.

12. The method of claim 1 , further comprising:
converting at least one of existing Double Diffusion Breaks (DDB) to a Half-DDB on the NFET side inside the FinFet cell using the cut-poly layer to isolate the PFET gates and the NFET gates; and
adding one or more PFET gate active fingers in a space created after removal of the DDB.

13. The method of claim 12 , further comprising:
removing one or more PFET fins for each transistor in the FinFet cell.

14. The method of claim 1 , further comprising:
converting at least one of some Double Diffusion Break to a Half-DDB on the NFET side inside the FinFet cell using the cut-poly layer to isolate the some PFET gates and the some NFET gates; and
creating at least two new PFET gates in a space created; and
converting at least one of the two new PFET gates into a Single Diffusion Break (SDB) and at least another of the two new PFET gates to a floating gate by connecting drain and source terminals to one of a common power net and a common internal net.

15. The method of claim 14 , wherein, when viewed from a plan view, a position of the at least one floating gate is one of to a left of the Single Diffusion Break and to a right of the Single Diffusion Break.

Assignees

• Samsung Electronics Co Ltd

Inventors

• AGARWAL Shyam
• Ghosh Abhishek
• Rana Parvinder Kumar

Classifications

• H01L27/11807 Primary

  Electricity · mapped topic

• H01L2027/11831

  Electricity · mapped topic

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title