Semiconductor device

Patent metadata

Field	Value
Publication number	US-12550447-B2
Application number	US-202318234942-A
Country	US
Kind code	B2
Filing date	Aug 17, 2023
Priority date	Feb 29, 2012
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

First claim

What is claimed is:

1 . A memory device comprising:
a first transistor; and a second transistor provided over the first transistor, wherein a gate electrode of the first transistor is electrically connected to a holding node, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected the holding node, wherein the second transistor comprises:
an oxide semiconductor layer comprising a channel formation region;
a gate insulating layer having a region being in contact with the oxide semiconductor layer;
a gate electrode layer having a region facing the oxide semiconductor layer with the gate insulating layer provided therebetween;
a first electrode layer being configured to be the one of the source electrode and the drain electrode of the second transistor; and
a second electrode layer being configured to be the other of the source electrode and the drain electrode of the second transistor,
wherein the second transistor is a vertical transistor, and wherein the holding node is configured to be written with data through the second transistor and hold the data by turning off the second transistor.

2 . The memory device according to claim 1 , wherein, in a top view, a region where the oxide semiconductor layer and the first electrode layer are in contact is provided inside an outer periphery of the first electrode layer.

3 . The memory device according to claim 1 , wherein, in a top view, the region of the gate electrode layer surrounds an outer periphery of the oxide semiconductor layer.

4 . The memory device according to claim 1 , wherein the second electrode layer is provided over the first electrode layer.

5 . The memory device according to claim 1 , wherein the second electrode layer has a region overlapping with the first electrode layer.

6 . The memory device according to claim 1 , wherein, in a cross-sectional view, the region of the gate electrode layer is located between the first electrode layer and the second electrode layer.

7 . The memory device according to claim 1 , wherein the channel formation region of the second transistor overlaps with a channel formation region of the first transistor.

8 . The memory device according to claim 1 , wherein the oxide semiconductor layer has a region comprising an intrinsic type or substantially intrinsic type oxide semiconductor.

9 . The memory device according to claim 1 ,
wherein the oxide semiconductor layer includes a crystal portion, wherein, in the crystal portion, a c-axis is aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed, and wherein in the direction parallel to the normal vector, an angle formed by the normal vector and the c-axis includes a range of −5° or more and 5° or less.

10 . The memory device according to claim 1 , wherein the oxide semiconductor layer comprises one of an indium oxide, a tin oxide, a zinc oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, and an In—Hf—Al—Zn-based oxide.

11 . The memory device according to claim 1 ,
wherein a direction of a channel length of the second transistor is perpendicular to an upper surface of the first electrode layer, and wherein an angle of perpendicular includes a range from 85° to 95°.

12 . The memory device according to claim 1 , wherein an outer periphery of the oxide semiconductor layer is circular in a plane parallel to an upper surface of the first electrode layer.

13 . The memory device according to claim 1 , wherein an outer periphery of the oxide semiconductor layer is polygonal in a plane parallel to an upper surface of the first electrode layer.

14 . A semiconductor device comprising:
a driver circuit; and one or a plurality of memory layers stacked over the driver circuit, wherein each of the memory layers comprises the memory device according to claim 2 .

15 . The memory device according to claim 1 , further comprising:
a first wiring provided over the second transistor; and a second wiring provided over the second transistor, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring via a first connection electrode layer, and wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring via a second connection electrode layer.

16 . The memory device according to claim 1 , further comprising:
a third wiring provided over the second transistor, wherein the third wiring has a region overlapping with the second electrode layer with an insulating layer provided therebetween, and wherein the second electrode layer is electrically connected to the third wiring via a third connection electrode layer.

17 . The memory device according to claim 1 , further comprising:
an interlayer insulating layer provided over the second transistor; and a third transistor having a region overlapping with the second transistor with the interlayer insulating layer, wherein the third transistor is a vertical transistor.

18 . A memory device comprising:
a first transistor; and a second transistor provided over the first transistor, wherein a gate electrode of the first transistor is electrically connected to a holding node, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected the holding node, wherein the second transistor comprises:
an oxide semiconductor layer comprising a channel formation region;
a gate insulating layer having a region being in contact with the oxide semiconductor layer;
a gate electrode layer having a region facing the oxide semiconductor layer with the gate insulating layer provided therebetween;
a first electrode layer being configured to be the one of the source electrode and the drain electrode of the second transistor; and
a second electrode layer being configured to be the other of the source electrode and the drain electrode of the second transistor,
wherein the gate insulating layer of the second transistor has a part having a cylindrical shape, wherein the second transistor is a vertical transistor, and wherein the holding node is configured to be written with data through the second transistor and hold the data by turning off the second transistor.

19 . The memory device according to claim 18 , wherein, in a top view, a region where the oxide semiconductor layer and the first electrode layer are in contact is provided inside an outer periphery of the first electrode layer.

20 . The memory device according to claim 18 , wherein, in a top view, the region of the gate electrode layer surrounds an outer periphery of the oxide semico

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Yoshizumi Kensuke

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10B12/00 Primary

  Dynamic random access memory [DRAM] devices · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D62/80

  characterised by the materials · CPC title