Semiconductor device

Patent metadata

Field	Value
Publication number	US-9312257-B2
Application number	US-201313768753-A
Country	US
Kind code	B2
Filing date	Feb 15, 2013
Priority date	Feb 29, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor comprising a first semiconductor layer; and
a second transistor being over and overlapping with the first transistor,
wherein a channel length direction between source and drain regions of the second transistor is perpendicular to an upper surface of the first semiconductor layer.

2. The semiconductor device according to claim 1 , further comprising a capacitor which is located over and overlaps with the first transistor.

3. The semiconductor device according to claim 1 , wherein a channel in the first semiconductor layer overlaps with the channel of the second transistor.

4. The semiconductor device according to claim 1 , wherein the first transistor is located over an insulating surface.

5. The semiconductor device according to claim 1 ,
wherein the first transistor further comprises:
a first insulating layer over the first semiconductor layer; and
a first electrode layer over the first insulating layer, and

wherein the second transistor comprises:
a second semiconductor layer in direct contact with the first electrode layer;
a second insulating layer adjacent to a side surface of the second semiconductor layer;
a second electrode layer adjacent to the side surface of the second semiconductor layer with the second insulating layer therebetween; and
a third electrode layer over the second semiconductor layer.

6. The semiconductor device according to claim 5 , wherein the second electrode layer is located between the first electrode layer and the third electrode layer.

7. The semiconductor device according to claim 5 ,
wherein the second semiconductor layer comprises an oxide semiconductor, and
wherein the first semiconductor layer comprises a material selected from single crystalline silicon, amorphous silicon, and polycrystalline silicon.

8. The semiconductor device according to claim 5 , further comprising a capacitor which comprises:
a dielectric layer in direct contact with the first electrode layer; and
a fourth electrode layer over the dielectric layer.

9. The semiconductor device according to claim 8 , wherein the second semiconductor layer and the dielectric layer exist in the same layer.

10. The semiconductor device according to claim 8 , wherein the second insulating layer and the dielectric layer exist in the same layer.

11. The semiconductor device according to claim 8 , wherein the second insulating layer and the second electrode layer surround the second semiconductor layer.

12. An electronic device comprising the semiconductor device according to claim 1 .

13. A semiconductor device comprising:
a first semiconductor layer;
a first insulating layer over the first semiconductor layer;
a first electrode layer over the first insulating layer;
a second semiconductor layer over and in direct contact with the first electrode layer;
a second insulating layer adjacent to a side surface of the second semiconductor layer;
a second electrode layer adjacent to the side surface of the second semiconductor layer with the second insulating layer therebetween; and
a third electrode layer over and in direct contact with the second semiconductor layer.

14. The semiconductor device according to claim 13 , wherein a channel in the first semiconductor layer overlaps with a channel in the second semiconductor layer.

15. The semiconductor device according to claim 13 , wherein the second electrode layer is located between the first electrode layer and the third electrode layer.

16. The semiconductor device according to claim 13 , wherein the first semiconductor layer is located over an insulating surface.

17. The semiconductor device according to claim 13 , wherein the second insulating layer and the second electrode layer surround the second semiconductor layer.

18. The semiconductor device according to claim 13 ,
wherein the second semiconductor layer comprises an oxide semiconductor, and
wherein the first semiconductor layer comprises a material selected from single crystalline silicon, amorphous silicon, and polycrystalline silicon.

19. The semiconductor device according to claim 13 , further comprising:
a dielectric layer over and in direct contact with the first electrode layer; and
a fourth electrode layer over the dielectric layer.

20. The semiconductor device according to claim 19 , wherein the second semiconductor layer and the dielectric layer exist in the same layer.

21. The semiconductor device according to claim 19 , wherein the second insulating layer and the dielectric layer exist in the same layer.

22. An electronic device comprising the semiconductor device according to claim 13 .

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Yoshizumi Kensuke

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title