Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9240467-B2
Application number	US-201514609833-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Dec 4, 2009
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;
forming a source electrode and a drain electrode over and in contact with the oxide semiconductor layer, wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and
removing an upper surface region and side surface regions of the oxide semiconductor layer at the uncovered part of the oxide semiconductor layer,
wherein the crystal region has a c-axis orientation.

2. The method according to claim 1 , further comprising the steps of:
adding oxygen into the oxide semiconductor layer; and
performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

3. The method according to claim 1 , further comprising the step of heating the oxide semiconductor layer, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×10 19 /cm 3 after heating the oxide semiconductor layer.

4. The method according to claim 1 , wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

5. The method according to claim 1 , wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.

6. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;
forming a conductive film over and in contact with the oxide semiconductor layer;
forming a source electrode and a drain electrode by selectively etching the conductive film, wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and
removing an upper surface region and side surface regions at the uncovered part of the oxide semiconductor layer,
wherein the crystal region has a c-axis orientation.

7. The method according to claim 6 , wherein the conductive film is selectively etched by wet etching.

8. The method according to claim 6 , further comprising the steps of:
adding oxygen into the oxide semiconductor layer; and
performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

9. The method according to claim 6 , further comprising the step of heating the oxide semiconductor layer, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×10 19 /cm 3 after heating the oxide semiconductor layer.

10. The method according to claim 6 , wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

11. The method according to claim 6 , wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.

12. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;
forming a source electrode and a drain electrode over and in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer extends beyond side edges of the source electrode and side edges of the drain electrode in a channel width direction, and wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and
removing an upper surface region and side surface regions of the oxide semiconductor layer at the uncovered part of the oxide semiconductor layer,
wherein the crystal region has a c-axis orientation.

13. The method according to claim 12 , further comprising the steps of:
adding oxygen into the oxide semiconductor layer; and
performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

14. The method according to claim 12 , further comprising the step of heating the oxide semiconductor layer, wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×10 19 /cm 3 after heating the oxide semiconductor layer.

15. The method according to claim 12 , wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

16. The method according to claim 12 , wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakata Junichiro
• Ohara Hiroki

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title