Semiconductor device

Patent metadata

Field	Value
Publication number	US-9349735-B2
Application number	US-201313905178-A
Country	US
Kind code	B2
Filing date	May 30, 2013
Priority date	Dec 25, 2009
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first transistor comprising:
a channel formation region comprising a semiconductor material;
a first gate insulating layer over the channel formation region; and
a first gate electrode over the first gate insulating layer,

an interlayer insulating film over the first transistor; and
a second transistor over the interlayer insulating film, the second transistor comprising:
a first oxide semiconductor layer over the interlayer insulating film;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode and a drain electrode over and in contact with the second oxide semiconductor layer;
a gate insulating layer over the source electrode and the drain electrode; and
a gate electrode over the gate insulating layer,

wherein an edge portion of each of the source electrode and the drain electrode is tapered, and
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer contains the same component.

2. The semiconductor device according to claim 1 , further comprising:
a first oxide region in contact with a side surface of the source electrode; and
a second oxide region in contact with a side surface of the drain electrode.

3. The semiconductor device according to claim 1 , further comprising:
a first insulating layer between the source electrode and the gate insulating layer; and
a second insulating layer between the drain electrode and the gate insulating layer.

4. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer is thicker than the first oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, zinc, and oxygen.

6. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is intrinsic.

7. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a crystal region.

8. A semiconductor device comprising:
a first transistor comprising:
a channel formation region comprising a semiconductor material;
a first gate insulating layer over the channel formation region; and
a first gate electrode over the first gate insulating layer,

an interlayer insulating film over the first transistor; and
a second transistor over the interlayer insulating film, the second transistor comprising:
a first oxide semiconductor layer over the interlayer insulating film;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode and a drain electrode over and in contact with the second oxide semiconductor layer;
a gate insulating layer over the source electrode and the drain electrode; and
a gate electrode over the gate insulating layer,

wherein an edge portion of each of the source electrode and the drain electrode is tapered.

9. The semiconductor device according to claim 8 , further comprising:
a first oxide region in contact with a side surface of the source electrode; and
a second oxide region in contact with a side surface of the drain electrode.

10. The semiconductor device according to claim 8 , further comprising:
a first insulating layer between the source electrode and the gate insulating layer; and
a second insulating layer between the drain electrode and the gate insulating layer.

11. The semiconductor device according to claim 8 , wherein the second oxide semiconductor layer is thicker than the first oxide semiconductor layer.

12. The semiconductor device according to claim 8 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, zinc, and oxygen.

13. The semiconductor device according to claim 8 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is intrinsic.

14. The semiconductor device according to claim 8 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises a crystal region.

15. A semiconductor device comprising:
a driver circuit comprising a first transistor, the first transistor comprising a channel formation region which comprises single crystal silicon;
a first insulating layer over the first transistor; and
a memory cell over the first insulating layer, the memory cell comprising:
a second transistor over the first insulating layer; and
a third transistor over the first insulating layer,

wherein each of the second transistor and the third transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the second transistor is electrically connected to one of a source or a drain of the third transistor, and
wherein the driver circuit is configured to drive the memory cell.

16. The semiconductor device according to claim 15 , wherein the oxide semiconductor comprises indium.

17. The semiconductor device according to claim 15 , further comprising a capacitor in the memory cell,
wherein one electrode of the capacitor is electrically connected to the gate of the second transistor.

18. The semiconductor device according to claim 15 , wherein the oxide semiconductor comprises a crystalline region.

19. The semiconductor device according to claim 15 , wherein the channel formation region of the first transistor is provided in an SOI substrate.

20. An electronic device comprising the semiconductor device according to claim 15 .

21. The semiconductor device according to claim 1 , wherein the channel formation region of the first transistor is provided in a semiconductor substrate.

22. The semiconductor device according to claim 8 , wherein the channel formation region of the first transistor is provided in a semiconductor substrate.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Kato Kiyoshi

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/003

  Cell access · CPC title

• H10B10/00

  Static random access memory [SRAM] devices · CPC title

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title