Vertical inverter formation on stacked field effect transistor (SFET)

Patent metadata

Field	Value
Publication number	US-12550427-B2
Application number	US-202217936416-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Sep 29, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

First claim

What is claimed is:

1 . A method for forming a semiconductor device, the method comprising:
forming a first nanosheet vertically stacked over a second nanosheet; forming a common gate around a channel region of the first nanosheet and a channel region of the second nanosheet; forming a top source or drain region in direct contact with the first nanosheet; and forming a bottom source or drain region in direct contact with the second nanosheet; wherein a first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region via a direct epitaxy contact growth of the first portion of the top source or drain region on a surface of the first portion of the bottom source or drain region to define a common source or drain region; and wherein a second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

2 . The method of claim 1 , further comprising:
forming a first nanosheet stack comprising the first nanosheet and one or more additional first nanosheets; and forming a second nanosheet stack comprising the second nanosheet and one or more additional second nanosheets.

3 . The method of claim 2 , wherein the semiconductor device comprises a stacked field effect transistor.

4 . The method of claim 3 , wherein the stacked field effect transistor comprises a complementary stacked field effect transistor comprising an nFET and a pFET.

5 . The method of claim 4 , wherein the first nanosheet stack defines a portion of one of the nFET and the pFET and the second nanosheet stack defines a portion of the other one of the nFET and the pFET.

6 . The method of claim 5 , further comprising forming a middle dielectric isolation structure between the first nanosheet and the second nanosheet, the middle dielectric isolation structure in direct contact with the common source or drain region.

7 . The method of claim 6 , wherein the top source or drain region comprises a first doping type and the bottom source or drain region comprises a second doping type opposite the first doping type.

8 . The method of claim 1 , wherein a first sidewall of the first nanosheet is coplanar to a first sidewall of the second nanosheet, and wherein a second sidewall of the first nanosheet is recessed with respect to a second sidewall of the second nanosheet.

9 . The method of claim 1 , further comprising forming a bottom source or drain contact on a surface of the bottom source or drain region.

10 . The method of claim 9 , further comprising forming an isolation structure between the bottom source or drain contact and the top source or drain region, wherein a portion of the isolation structure is between the bottom source or drain contact and the common gate.

11 . A semiconductor device comprising:
a first nanosheet vertically stacked over a second nanosheet; a common gate formed around a channel region of the first nanosheet and a channel region of the second nanosheet; a top source or drain region in direct contact with the first nanosheet; and a bottom source or drain region in direct contact with the second nanosheet; wherein a first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region via direct epitaxy contact between the first portion of the top source or drain region and a surface of the first portion of the bottom source or drain region to define a common source or drain region; and wherein a second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

12 . The semiconductor device of claim 11 , further comprising:
a first nanosheet stack comprising the first nanosheet and one or more additional first nanosheets; and a second nanosheet stack comprising the second nanosheet and one or more additional second nanosheets.

13 . The semiconductor device of claim 12 , wherein the semiconductor device comprises a stacked field effect transistor.

14 . The semiconductor device of claim 13 , wherein the stacked field effect transistor comprises a complementary stacked field effect transistor comprising an nFET and a pFET.

15 . The semiconductor device of claim 14 , wherein the first nanosheet stack defines a portion of one of the nFET and the pFET and the second nanosheet stack defines a portion of the other one of the nFET and the pFET.

16 . The semiconductor device of claim 15 , further comprising a middle dielectric isolation structure between the first nanosheet and the second nanosheet, the middle dielectric isolation structure in direct contact with the common source or drain region.

17 . The semiconductor device of claim 16 , wherein the top source or drain region comprises a first doping type and the bottom source or drain region comprises a second doping type opposite the first doping type.

18 . The semiconductor device of claim 16 , wherein a first sidewall of the first nanosheet is coplanar to a first sidewall of the second nanosheet, and wherein a second sidewall of the first nanosheet is recessed with respect to a second sidewall of the second nanosheet.

19 . The semiconductor device of claim 11 , further comprising a bottom source or drain contact on a surface of the bottom source or drain region.

20 . The semiconductor device of claim 19 , further comprising an isolation structure between the bottom source or drain contact and the top source or drain region, wherein a portion of the isolation structure is between the bottom source or drain contact and the common gate.

Assignees

• IBM

Inventors

• Sung Min Gyu
• Frougier Julien
• Cheng Kangguo
• Xie Ruilong
• Park Chanro

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title