Nanosheet-CMOS EPROM device with epitaxial oxide charge storage region

Patent metadata

Field	Value
Publication number	US-10916629-B2
Application number	US-201816050810-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a nanosheet stack comprising an epitaxial oxide nanosheet sandwiched between a first silicon channel material nanosheet, wherein the nanosheet stack is suspended above a semiconductor substrate, and the epitaxial oxide nanosheet has a first surface that is in direct physical contact with an entirety of a surface of the first silicon channel material nanosheet, and a second surface, which is opposite the first surface, that is in direct physical contact with an entirety of a surface of the second silicon channel material nanosheet;
a first field effect transistor of a first conductivity type located beneath the first silicon channel material nanosheet;
a second field effect transistor of a second conductivity type, opposite the first conductivity type, located above the second silicon channel material nanosheet;
a first source/drain structure located on each side of the nanosheet stack and in direct physical contact with a sidewall of the first silicon channel material nanosheet and a lower portion of a sidewall of the epitaxial oxide nanosheet; and
a second source/drain structure located on each side of the nanosheet stack and in direct physical contact with a sidewall of the second silicon channel material nanosheet and an upper portion of the sidewall of the epitaxial oxide nanosheet.

2. The semiconductor structure of claim 1 , wherein electrons are stored in the epitaxial oxide nanosheet.

3. The semiconductor structure of claim 1 , wherein the epitaxial oxide nanosheet, the first silicon channel material nanosheet and the second silicon channel material nanosheet are lattice matched.

4. The semiconductor structure of claim 1 , wherein the sidewalls of the epitaxial oxide nanosheet are vertically aligned to the sidewalls of both the first silicon channel material nanosheet and the second silicon channel material.

5. The semiconductor structure of claim 1 , further comprising an inner spacer surrounding the first field effect transistor and another inner spacer surrounding the second field effect transistor.

6. The semiconductor structure of claim 1 , further comprising a dielectric material layer separating the first and second source/drain structures, and directly contacting a middle portion of the sidewall of the epitaxial oxide nanosheet.

7. The semiconductor structure of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

8. The semiconductor structure of claim 3 , wherein the epitaxial oxide nanosheet is composed of lanthanum (II) oxide, gadolinium(III)-oxide, dysprosium(III)-oxide, holmium(III) oxide, erbium (III) oxide, thulium (III) oxide, lutetium(III) oxide, cerium (IV) oxide, lanthanum-yttrium oxide, gadolinium-erbium oxide, neodymium-erbium oxide, neodymium-gadolinium oxide, or lanthanum-erbium oxide.

9. The semiconductor structure of claim 1 , further comprising a dielectric isolation structure located on the semiconductor substrate.

Assignees

• IBM

Inventors

• Reznicek Alexander
• Yau Jeng-Bang
• Ning Tak H
• Shahidi Ghavam G

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title