Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices

Patent metadata

Field	Value
Publication number	US-10741641-B2
Application number	US-201816013247-A
Country	US
Kind code	B2
Filing date	Jun 20, 2018
Priority date	Jun 20, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.

First claim

What is claimed is:

1. A method for forming a complementary metal oxide semiconductor (CMOS) device, the method comprising:
epitaxially growing a multilayer structure on a substrate in an NFET region and a PFET region, the multilayer structure comprising alternating silicon layers, with a silicon layer sandwiched between SiGe(x) layers, and SiGe(x+25) layers sandwiched between the SiGe(x) layers, wherein a bottommost layer is a sacrificial dielectric isolation layer comprising the SiGe(x+25), wherein the sacrificial dielectric isolation layer is at thickness greater than each of the SiGe(x+25) layers sandwiched between the SiGe(x) layers, wherein (x) is from about 5 atomic percent to about 50 atomic percent;
patterning the multilayer structure to form one or more nanosheet stacks in the NFET region and the PFET region;
selectively removing the SiGe(x+25) layers from each of the nanosheet stacks in both the NFET and PFET regions, wherein selectively removing the SiGe(x+25) layers forms a space between each SiGe(x) layer of the multilayer structure and the substrate and a lowermost one of the SiGe(x) layers;
conformally depositing an oxide layer on the substrate, wherein the oxide layer is at a thickness effective to fill the space between each of the SiGe(x) layers and forming the oxide layer on the substrate;
conformally depositing a nitride layer on the substrate, wherein the nitride layer is at a thickness effective to fill the space between the lowermost one of the SiGe(x) layers and the substrate;
selectively removing the nitride layer such that the nitride layer remains in the space between the lowermost one of the SiGe(x) layers and the substrate;
blocking the PFET region with a block mask followed by removing the oxide layer and SiGe(x) layers from the at least one or more nanosheet stacks in the NFET region;
removing the block mask from the PFET region and heating the substrate to diffuse the germanium in each SiGe(x) layer into each silicon layer to form germanium diffused silicon layers in the PFET region;
blocking the NFET region with a block mask followed by removing the oxide layer and thinning each germanium diffused silicon layer from the nanosheet stack in the NFET region; and
removing the block mask from the NFET region.

2. The method of claim 1 , wherein the block mask in the PFET region comprises depositing an organic planarizing layer onto the substrate, and lithographically patterning the organic planarizing layer to open the NFET region.

3. The method of claim 1 , wherein the block mask in the NFET region comprises depositing an organic planarizing layer onto the substrate, and lithographically patterning the organic planarizing layer to open the PFET region.

4. The method of claim 1 , wherein selectively removing the SiGe(x+25) layers from each of the nanosheet stacks in both the NFET and PFET regions comprises exposing the SiGe(x+25) layers to HCl vapor.

5. The method of claim 1 , wherein (x) is from about 10 atomic percent to about 40 atomic percent.

6. The method of claim 1 , wherein (x) is from about 20 atomic percent to about 30 atomic percent.

7. The method of claim 1 , wherein removing the oxide layer in the PFET region and the NFET region comprises exposing the exposed surfaces of the oxide layer to a buffered hydrofluoric acid etch process.

8. The method of claim 1 , wherein the SiGe(x) and the SiGe(x+25) layers are each at a thickness of about 2 to about 4 nm, the silicon layer is at a thickness of about 4 nm to about 8 nm; and the sacrificial dielectric isolation layer is at a thickness of about 8 nm to about 12 nm.

9. The method of claim 1 , wherein the oxide layers and the nitride layers are deposited by atomic layer deposition.

10. The method of claim 1 , wherein the heating the substrate to diffuse the germanium is at a temperature of about 800° C. to 1000° C. for about 4 second to 10 minutes.

11. A method for forming nanochannels in a complementary metal oxide semiconductor (CMOS) device, the method comprising:
epitaxially growing a sacrificial dielectric isolation layer at a thickness of about 8 nm to about 12 nm on a substrate, wherein the sacrificial dielectric isolation layer comprises SiGe(x+25);
epitaxially growing a multilayer structure on the sacrificial dielectric isolation layer, the multilayer structure comprising alternating silicon layers each at a thickness of about 4 nm to 8 nm sandwiched between SiGe(x) layers at a thickness of about 2 nm to 4 nm, and SiGe(x+25) layers at a thickness of about 2 nm to about 4 nm sandwiched between each of the SiGe(x) layers;
patterning the multilayer structure to form one or more nanosheet stacks in an NFET region and a PFET region;
selectively removing the SiGe(x+25) layers to form a first space between the SiGe(x) layers and a second space from between the sacrificial dielectric isolation region and the substrate;
conformally depositing an oxide layer at a thickness effective to fill each first space between the SiGe(x) layers;
conformally depositing a nitride layer on the substrate and at a thickness effective to fill the second space;
removing the nitride layer from surfaces other than the second space such that the nitride layer fills the second space and forms a dielectric isolation region between the substrate and each of the nanosheet stacks;
blocking the PFET region with a block mask followed by removing the oxide layer and the SiGe(x) layers from the one or more nanosheet stacks in the NFET region;
removing the block mask from the PFET region and heating the substrate to diffuse the germanium in the SiGe(x) layer into the silicon layer to form a germanium diffused silicon layer in the PFET region;
blocking the NFET region with a block mask followed by removing the oxide layer and thinning the germanium diffused silicon layer from the nanosheet stack in the NFET region; and
removing the block mask from the NFET region.

12. The method of claim 11 , wherein the NFET region is separated from the PFET region by a shallow trench isolation region in the substrate.

13. The method of claim 11 , wherein the oxide layers and the nitride layers are deposited by atomic layer deposition.

14. The method of claim 11 , wherein selectively removing the SiGe(x+25) layers is at an etch selectivity greater than 30:1 relative to the SiGe(x) layers.

15. The method of claim 11 , wherein selectively removing the SiGe(x) layers comprises exposing the SiGe(x) layers to an HCl vapor.

16. The method of claim 11 further comprising thinning the germanium diffused silicon layer in the PFET region with a wet etch process.

17. A method for forming nanochannels in a complementary metal oxide semiconductor (CMOS) device, the method comprising:
epitaxially growing a sacrificial dielectric isolation layer at a thickness of about 8 nm to about 12 nm on a substrate, wherein the sacrificial dielectric isolation layer comprises SiGe(x+25);
epitaxially growing a multilayer structure on the sacrificial dielectric isolation layer, the multilayer structure comprising alternating silicon layers each at a thickness of about 4 nm to 8 nm sandwiched between SiGe(x) layers at a thickness of about 2 nm to 4 nm, and SiGe(x+25) layers at a thickness of about 2 nm to about 4 nm sandwiched between the SiGe(x) layers;
patterning the multilayer structure to form one or more nanosheet stacks in an NFET region and a PFET region;
selectively removing the SiGe(x+25) layers material layers to form a first space between each of the SiGe(x) layers and a second space between the sacrificial dielectric isolation region and th

Assignees

• IBM

Inventors

• Guillorn Michael A
• Loubet Nicolas

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title