Contact formation to 3D monolithic stacked FinFETs

Patent metadata

Field	Value
Publication number	US-9659963-B2
Application number	US-201514753908-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jun 29, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A first gate structure straddles one end of a staircase fin stack that contains a first semiconductor material fin, an insulator fin, and a second semiconductor material fin, a second gate structure straddles a portion of the staircase fin stack, a third gate structure straddles another end of the staircase fin stack, and a fourth gate structure straddles a portion of only the first semiconductor fin. A first contact structure is between the first and second gate structures, a second contact structure is between the second and third gate structures, and a third contact structure is between the third and fourth gate structures. The first contact structure has a contact metal that contacts the first and second semiconductor material fins. The second contact structure has a contact metal that contacts only the second semiconductor material fin, and the third contact structure has a contact metal that contacts only the first semiconductor fin.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a staircase fin stack extending upwards from a substrate and comprising, from bottom to top, a first semiconductor material fin, an insulator fin, and a second semiconductor material fin;
a first gate structure straddling over a first portion of said staircase fin stack, a second gate structure straddling over a second portion of said staircase fin stack, a third gate structure straddling over a third portion of said staircase fin stack, and a fourth gate structure straddling over an exposed portion of only said first semiconductor material fin;
an interlevel dielectric material surrounding said first gate structure, said second gate structure, said third gate structure and said fourth gate structure; and
a first contact structure located in a first portion of said interlevel dielectric material and between said first gate structure and said second gate structure, a second contact structure located in a second portion of said interlevel dielectric material and between said second gate structure and said third gate structure, and a third contact structure located in a third portion of said interlevel dielectric material and between said third gate structure and said fourth gate structure, wherein said first contact structure has a contact metal contacting said second semiconductor material fin and said first semiconductor material fin of said staircase fin stack, said second contact structure has a contact metal that contacts only said second semiconductor material fin, and said third contact structure has a contact metal that contacts only said first semiconductor material fin.

2. The semiconductor structure of claim 1 , wherein said substrate comprising an insulator layer located directly beneath said first semiconductor material fin, and a handle substrate located directly beneath said insulator layer.

3. The semiconductor structure of claim 1 , wherein said first contact structure further comprises an upper epitaxial semiconductor material located between a first portion of said metal contact and said second semiconductor material fin and a lower epitaxial semiconductor material located between a second portion of said metal contact and said first semiconductor material fin.

4. The semiconductor structure of claim 3 , wherein said second contact structure further comprises an upper epitaxial semiconductor material located between said metal contact and said second semiconductor material fin and a lower epitaxial semiconductor material located on said first semiconductor material fin.

5. The semiconductor structure of claim 4 , wherein said third contact structure further comprises a lower epitaxial semiconductor material located between said contact metal and said first semiconductor material fin.

6. The semiconductor structure of claim 1 , wherein a topmost surface of said interlevel dielectric material is coplanar with a topmost surface of each of said first contact structure, said second contact structure, and said third contact structure.

7. The semiconductor structure of claim 1 , wherein a gate dielectric spacer is located on sidewall surfaces of said first gate structure, said second gate structure, said third gate structure, and said fourth gate structure.

8. The semiconductor structure of claim 1 , wherein said first semiconductor material fin has a length and a width that is greater than a length and a width of both said insulator fin and said second semiconductor material fin.

9. The semiconductor structure of claim 1 , wherein a portion of said first gate structure lands on a topmost surface of said second semiconductor material fin and another portion of said first gate structure lands on a portion of said substrate.

10. The semiconductor structure of claim 9 , wherein a portion of said third gate structure lands on a topmost surface of said second semiconductor material fin and another portion of said third gate structure lands on a portion of said first semiconductor material fin.

11. A method of forming a semiconductor structure, said method comprising:
forming a staircase fin stack extending upwards from a substrate and comprising, from bottom to top, a first semiconductor material fin, an insulator fin, and a second semiconductor material fin;
forming, in any order, a first gate structure straddling over a first portion of said staircase fin stack, a second gate structure straddling over a second portion of said staircase fin stack, a third gate structure straddling over a third portion of said staircase fin stack, and a fourth gate structure straddling over an exposed portion of only said first semiconductor material fin;
forming an interlevel dielectric material surrounding said first gate structure, said second gate structure, said third gate structure and said fourth gate structure; and
forming, in any order, a first contact structure in a first portion of said interlevel dielectric material and between said first gate structure and said second gate structure, a second contact structure in a second portion of said interlevel dielectric material and between said second gate structure and said third gate structure, and a third contact structure in a third portion of said interlevel dielectric material and between said third gate structure and said fourth gate structure, wherein said first contact structure has a contact metal contacting said second semiconductor material fin and said first semiconductor material fin of said staircase fin stack, said a second contact structure has a contact metal that contacts only said second semiconductor material fin and said third contact structure has a contact metal that contacts only said first semiconductor material fin.

12. The method of claim 11 , wherein said forming said staircase fin stack comprises:
providing a structure comprising, from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, a second insulator layer, and a second semiconductor material layer;
patterning said second semiconductor material layer, said second insulator layer and said first semiconductor material layer to provide a non-staircase fin stack of, from bottom to top, a remaining portion of said first semiconductor material layer, a remaining portion of said second insulator layer and a remaining portion of said second semiconductor material layer; and
etching a portion of said remaining portion of said second semiconductor material layer to provide said second semiconductor material fin and a portion of said remaining portion of said second insulator to provide said insulator fin, and wherein said remaining portion of said first semiconductor material provides said first semiconductor material fin.

13. The method of claim 12 , wherein said patterning comprises a sidewall image transfer process.

14. The method of claim 11 , further comprising forming a gate dielectric spacer on each sidewall surface of said first gate structure, said second gate structure, said third gate structure and said fourth gate structure prior to forming said interlevel dielectric material.

15. The method of claim 11 , wherein said forming said first contact structure further comprises forming an upper epitaxial semiconductor material between a first portion of said metal contact and said second semiconductor material fin and forming a lower epitaxial semiconductor material between a second portion of said metal contact and said first semiconductor material fin.

16. The method of claim 15 , wherein said forming said second contact structure further comprises forming an upper epitaxia

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H01L21/30604

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic