Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication

Patent metadata

Field	Value
Publication number	US-10964706-B2
Application number	US-201916450550-A
Country	US
Kind code	B2
Filing date	Jun 24, 2019
Priority date	Jul 19, 2016
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first layer of nanosheets;
a second layer of nanosheets positioned above the first layer of nanosheets;
a third layer of nanosheets positioned above the second layer of nanosheets, wherein the first layer of nanosheets, the second layer of nanosheets, and the third layer of nanosheets include nanosheet portions positioned within a source-drain region of a semiconductor device;
a first electrode that connects the first layer of nanosheets and is routed through the source-drain region to a first position above the source-drain region;
a second electrode that connects the second layer of nanosheets and is routed through the source-drain region to a second position above the source-drain region;
a third electrode that connects the third layer of nanosheets and is routed through the source-drain region to a third position above the source-drain region;
wherein at least one of the electrodes is routed through the source-drain region by a first contact structure that is step-shaped with a portion of a second contact structure positioned above a horizontal surface of the respective electrode.

2. The semiconductor device of claim 1 , wherein the nanosheets include complimentary semiconductor material above each other.

3. The semiconductor device of claim 1 , wherein the step-shaped contact structure is positioned within the source-drain region and configured to electrically couple each layer of nanosheets to a position above the source-drain region.

4. The semiconductor device of claim 1 , wherein the first, second and third layers of nanosheets comprise a first field effect transistor (FET), a second FET and a third FET respectively, the third FET being formed on a third plane substantially parallel to the second and first layers, and being vertically spaced from the first and second layers.

5. The semiconductor device according to claim 1 , wherein the first electrode is separated from the second electrode by a dielectric film.

6. The semiconductor device according to claim 1 , wherein the second electrode is separated from the third electrode by a dielectric film.

7. The semiconductor device according to claim 1 , wherein the first layer of nanosheets comprises P-type Field Effect Transistor (PFET) wires.

8. The semiconductor device according to claim 1 , wherein the first layer of nanosheets comprises N-type Field Effect Transistor (NFET) wires.

9. The semiconductor device according to claim 1 , wherein the first layer of nanosheets comprises nanosheets of a different channel configuration than the nanosheets of the second layer.

10. The semiconductor device according to claim 1 , wherein the nanosheets are silicon-germanium (SiGe) nanosheets.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Devilliers Anton J

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/021 Primary

  of interconnections within wafers or substrates · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title