Structure containing first and second vertically stacked nanosheets having different crystallographic orientations

Patent metadata

Field	Value
Publication number	US-9887197-B2
Application number	US-201615257073-A
Country	US
Kind code	B2
Filing date	Sep 6, 2016
Priority date	Dec 19, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A semiconductor structure is provided that includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a first device region and a second device region. First vertically stacked and suspended nanosheets of semiconductor channel material of the first crystallographic orientation are located above the substrate and within the first device region. Second vertically stacked and suspended nanosheets of semiconductor channel material of a second crystallographic orientation are located above the substrate and within the second device region. In accordance with the present application, the second crystallographic orientation is different from the first crystallographic orientation.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate comprising a first semiconductor material having a first crystallographic orientation and a first device region and a second device region;
first vertically stacked and suspended nanosheets of a semiconductor channel material of said first crystallographic orientation located above said substrate and within said first device region; and
second vertically stacked and suspended nanosheets of a semiconductor channel material of a second crystallographic orientation located above said substrate and within said second device region, wherein said second crystallographic orientation is different from said first crystallographic orientation.

2. The semiconductor structure of claim 1 , further comprising a first epitaxial semiconductor S/D structure located on sidewall surfaces of said first vertically stacked and suspended nanosheets of said semiconductor channel material of said first crystallographic orientation, and a second epitaxial semiconductor S/D structure located on sidewall surfaces of said second vertically stacked and suspended nanosheets of said semiconductor channel material of said second crystallographic orientation.

3. The semiconductor structure of claim 2 , wherein said first epitaxial semiconductor S/D structure and said second epitaxial semiconductor S/D structure comprises a semiconductor material and a dopant selected from the group consisting of an n-type dopant or a p-type dopant.

4. The semiconductor structure of claim 3 , wherein said dopant of said first epitaxial semiconductor S/D structure is of a different conductivity type than said dopant of said second epitaxial semiconductor S/D structure.

5. The semiconductor structure of claim 1 , wherein each semiconductor channel material of said first vertically stacked and suspended nanosheets of said semiconductor channel material and said second vertically stacked and suspended nanosheets of said semiconductor channel material is composed of silicon.

6. The semiconductor structure of claim 5 , wherein said first crystallographic orientation is {100} and said second crystallographic orientation is {110}.

7. The semiconductor structure of claim 5 , wherein said first crystallographic orientation is {110} and said second crystallographic orientation is {100}.

8. The semiconductor structure of claim 1 , further comprising an insulator layer located directly on an entirety of said substrate in said first and second device regions.

9. The semiconductor structure of claim 1 , further comprising an insulator layer located directly on said substrate in said first device region, and a substrate portion of a second semiconductor material having said second crystallographic orientation that is present on said substrate in said second device region, wherein a portion of said oxide layer extends onto said substrate portion.

10. The semiconductor structure of claim 1 , further comprising a first functional gate structure surrounding said first vertically stacked and suspended nanosheets of said semiconductor channel material and a second functional gate structure surrounding said second vertically stacked and suspended nanosheets of said semiconductor channel material.

11. The semiconductor structure of claim 10 , wherein said first functional gate structure is a pFET and said second functional gate structure is a nFET.

12. The semiconductor structure of claim 11 , wherein said first crystallographic orientation is {110} and said second crystallographic orientation is {100}, and wherein each semiconductor channel material of said first vertically stacked and suspended nanosheets of said semiconductor channel material comprises a relaxed semiconductor material, and each semiconductor channel material of said second vertically stacked and suspended nanosheets of said semiconductor channel material comprises a strained semiconductor material.

13. The semiconductor structure of claim 10 , further comprising a middle-of-the-line (MOL) dielectric material surrounding said first functional gate structure and said second functional gate structure, wherein a topmost surface of said MOL dielectric is coplanar with a topmost surface of said first and second functional gate structures.

14. The semiconductor structure of claim 13 , wherein a topmost surface of said first and second vertically stacked and suspended nanosheets of said semiconductor channel materials is located beneath said topmost surface of said MOL dielectric material.

15. The semiconductor structure of claim 1 , wherein each semiconductor channel material of said first and second vertically stacked and suspended nanosheets of said semiconductor channel material comprises a same semiconductor material.

16. The semiconductor structure of claim 1 , wherein at least one semiconductor channel material of said first and second vertically stacked and suspended nanosheets of said semiconductor channel materials comprises a different semiconductor material than at least one other semiconductor channel material.

17. The semiconductor structure of claim 1 , wherein each semiconductor channel material of said first vertically stacked and suspended nanosheets of said semiconductor channel material is comprised of a relaxed semiconductor material, and each semiconductor channel material of said second vertically stacked and suspended nanosheets of said semiconductor channel material is comprised of a strained semiconductor material.

18. The semiconductor structure of claim 1 , wherein each semiconductor channel material of said first vertically stacked and suspended nanosheets of said semiconductor channel material is comprised of a strained semiconductor material, and each semiconductor channel material of said second vertically stacked and suspended nanosheets of said semiconductor channel material is comprised of a relaxed semiconductor material.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H01L21/823821

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H10D62/121

  oriented parallel to substrates · CPC title