Structures and SRAM bit cells integrating complementary field-effect transistors

Patent metadata

Field	Value
Publication number	US-10818674-B2
Application number	US-201916295485-A
Country	US
Kind code	B2
Filing date	Mar 7, 2019
Priority date	Mar 7, 2019
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

First claim

What is claimed is:

1. A structure comprising:
a static random access memory bit cell including a first complementary field-effect transistor and a second complementary field-effect transistor, the first complementary field-effect transistor including a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor, and the second complementary field-effect transistor including a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor, the first storage nanosheet transistor of the first complementary field-effect transistor includes a first source/drain region, the second storage nanosheet transistor of the first complementary field-effect transistor includes a second source/drain region arranged over the first source/drain region; and the first gate electrode and the second gate electrode are arranged in a first spaced arrangement along a longitudinal axis;
a conductive spacer aligned substantially parallel to the longitudinal axis, the conductive spacer coupled with the first source/drain region and the second source/drain region; and
a first access nanosheet transistor having a third gate electrode,
wherein the third gate electrode is aligned with the first gate electrode in a second spaced arrangement along the longitudinal axis.

2. The structure of claim 1 further comprising:
a local interconnect arranged to couple the conductive spacer with the second gate electrode of the second complementary field-effect transistor.

3. The structure of claim 1 further comprising:
a second access nanosheet transistor having a fourth gate electrode,
wherein the fourth gate electrode is aligned with the second gate electrode in a third spaced arrangement along the longitudinal axis, and the first gate electrode and the second gate electrode are laterally arranged between the third gate electrode and the fourth gate electrode.

4. The structure of claim 1 wherein the first access nanosheet transistor further includes a third source/drain region, and the conductive spacer couples the first source/drain region and the second source/drain region with the third source/drain region.

5. The structure of claim 4 further comprising:
an isolation layer comprised of a first dielectric material; and
a pillar comprised of a second dielectric material, the pillar extending in a vertical direction from the isolation layer,
wherein the first source/drain region, the second source/drain region, the third source/drain region, and the conductive spacer are arranged over the isolation layer adjacent to the pillar.

6. A structure comprising:
a static random access memory bit cell including a first complementary field-effect transistor and a second complementary field-effect transistor, the first complementary field-effect transistor including a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor, the second complementary field-effect transistor including a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor, the first storage nanosheet transistor of the first complementary field-effect transistor including a first source/drain region, and the second storage nanosheet transistor of the first complementary field-effect transistor including a second source/drain region arranged over the first source/drain region;
an isolation layer comprised of a first dielectric material; and
a pillar comprised of a second dielectric material, the pillar extending in a vertical direction from the isolation layer,
wherein the first gate electrode and the second gate electrode are arranged in a first spaced arrangement along a longitudinal axis, and the first source/drain region and the second source/drain region are arranged over the isolation layer and adjacent to the pillar.

7. The structure of claim 6 wherein the first source/drain region and the second source/drain region are in direct contact with the pillar.

8. The structure of claim 6 further comprising:
a conductive spacer aligned substantially parallel to the longitudinal axis, the conductive spacer coupled with the first source/drain region and the second source/drain region,
wherein the first source/drain region, the second source/drain region, and the conductive spacer are in direct contact with the pillar.

9. The structure of claim 8 further comprising:
a local interconnect arranged to couple the conductive spacer with the second gate electrode of the second complementary field-effect transistor.

10. The structure of claim 6 further comprising:
a first access nanosheet transistor having a third gate electrode,
wherein the third gate electrode is aligned with the first gate electrode in a second spaced arrangement along the longitudinal axis.

11. The structure of claim 10 further comprising:
a second access nanosheet transistor having a fourth gate electrode,
wherein the fourth gate electrode is aligned with the second gate electrode in a third spaced arrangement along the longitudinal axis, and the first gate electrode and the second gate electrode are laterally arranged between the third gate electrode and the fourth gate electrode.

12. A method comprising:
forming a first storage nanosheet transistor and a second storage nanosheet transistor that share a first gate electrode and that are stacked with the second storage nanosheet transistor arranged over the first storage nanosheet transistor;
forming a third storage nanosheet transistor and a fourth storage nanosheet transistor that share a second gate electrode and that are stacked with the fourth storage nanosheet transistor arranged over the third storage nanosheet transistor; and
forming a first access nanosheet transistor having a third gate electrode and a second access nanosheet transistor having a fourth gate electrode,
wherein the first storage nanosheet transistor and the second storage nanosheet transistor belong to a first complementary field-effect transistor of a static random access memory bit cell, the third storage nanosheet transistor and the fourth storage nanosheet transistor belong to a second complementary field-effect transistor of the static random access memory bit cell, and the first gate electrode and the second gate electrode are arranged in a first spaced arrangement along a longitudinal axis, the third gate electrode is aligned with the first gate electrode with a second spaced arrangement along the longitudinal axis, and the fourth gate electrode is aligned with the second gate electrode with a third spaced arrangement along the longitudinal axis.

13. The method of claim 12 wherein the first storage nanosheet transistor includes a first source/drain region and the second storage nanosheet transistor includes a second source/drain region, and further comprising:
forming a conductive spacer aligned substantially parallel to the longitudinal axis,
wherein the conductive spacer couples the first source/drain region with the second source/drain region.

14.

Assignees

• Globalfoundries Inc

Inventors

• Mann Randy W
• Paul Bipul C
• Frougier Julien
• Xie Ruilong

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title