Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS

Patent metadata

Field	Value
Publication number	US-10593673-B2
Application number	US-201815980250-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	May 15, 2018
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

First claim

What is claimed is:

1. A semiconductor structure comprising:
an nFET device region comprising an nFET nanosheet stack of suspended silicon channel material nanosheets located entirely above a p-type silicon punch through stop layer that is present directly on a first portion of a silicon substrate having a first height; and
a pFET device region located laterally adjacent the nFET device region and comprising a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets located entirely above an n-type doped silicon germanium alloy layer that is present directly on a second portion of the semiconductor substrate having a second height that is greater than the first height, wherein each suspended silicon channel material nanosheet in the nFET device region is vertically and horizontally off-set by one nanosheet from each silicon germanium alloy channel material nanosheet in the pFET device region, and the p-type silicon punch through stop layer is vertically and horizontally off-set from the n-type doped silicon germanium alloy layer, and wherein the n-type doped silicon germanium alloy layer has a topmost surface that is coplanar with a bottommost surface of a bottommost silicon channel material nanosheet of the suspended silicon channel material nanosheets and a bottommost surface that directly contacts the second portion of the semiconductor substrate and is coplanar with a topmost surface of the p-type silicon punch through stop layer.

2. The semiconductor structure of claim 1 , further comprising an nFET functional gate structure surrounding a portion of each suspended silicon channel material nanosheet, and a pFET functional gate structure surrounding a portion of each suspended silicon germanium alloy channel material nanosheet.

3. The semiconductor structure of claim 2 , further comprising an nFET inner spacer located between end portions of each suspended silicon channel material nanosheet, and a pFET inner spacer located between end portions of each suspended silicon germanium alloy channel material nanosheet.

4. The semiconductor structure of claim 3 , further comprising an nFET source/drain region on each side of the nFET nanosheet stack and physically contacting a sidewall of each suspended silicon channel material nanosheet, and a pFET source/drain region on each side of the pFET nanosheet stack and physically contacting a sidewall of each suspended silicon germanium alloy channel material nanosheet.

5. The semiconductor structure of claim 4 , wherein a gap is present between each nFET inner spacer and the nFET source/drain region, and a gap is present between each pFET inner spacer and the pFET source/drain region.

6. The semiconductor structure of claim 4 , wherein the nFET source/drain region is composed of phosphorus-doped silicon, and the pFET source/drain region is composed of a boron doped silicon germanium alloy.

7. The semiconductor structure of claim 2 , further comprising a first gate spacer located above a topmost silicon channel material nanosheet of the nFET nanosheet stack and surrounding an upper portion of the nFET functional gate structure that is located on the topmost silicon channel material nanosheet of the nFET nanosheet stack, and a second gate spacer located above a topmost silicon germanium alloy channel material nanosheet of the pFET nanosheet stack and surrounding an entirety of the pFET functional gate structure that is located on the topmost silicon germanium alloy channel material nanosheet of the pFET nanosheet stack.

8. The semiconductor structure of claim 4 , further comprising a first source/drain contact structure contacting a surface of the nFET source/drain region, and a second source/drain contact structure contacting a surface of the pFET source/drain region.

9. The semiconductor structure of claim 1 , wherein the p-type silicon punch through stop layer has a p-type dopant concentration from 1E17 atoms/cm 3 to 1E20 atoms/cm 3 .

10. The semiconductor structure of claim 5 , wherein the n-type doped silicon germanium alloy layer is composed of a phosphorus doped silicon germanium alloy.

11. The semiconductor structure of claim 7 , wherein the first gate spacer located above the topmost silicon channel material nanosheet of the nFET nanosheet stack has a topmost surface that is vertical offset, and located above, a topmost surface of the nFET functional gate structure that is located on the topmost silicon channel material nanosheet of the nFET nanosheet stack.

12. The semiconductor structure of claim 11 , further comprising a dielectric capping material located on the topmost surface of the nFET functional gate structure that is located on the topmost silicon channel material nanosheet of the nFET nanosheet stack, wherein the dielectric capping material has a topmost surface that is coplanar with the topmost surface of the first spacer.

13. The semiconductor structure of claim 7 , wherein the second gate spacer located above the topmost silicon germanium alloy channel material nanosheet of the pFET nanosheet stack has a topmost surface that is vertical offset, and located above, a topmost surface of the pFET functional gate structure that is located on the topmost silicon germanium alloy channel material nanosheet of the pFET nanosheet stack.

14. The semiconductor structure of claim 13 , further comprising a dielectric capping material located on the topmost surface of the pFET functional gate structure that is located on the topmost silicon germanium alloy channel material nanosheet of the pFET nanosheet stack, wherein the dielectric capping material has a topmost surface that is coplanar with the topmost surface of the second spacer.

Assignees

• IBM

Inventors

• Miao Xin
• Zhang Jingyun
• Reznicek Alexander
• Lee Choonghyun

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L27/0922 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic