Three-dimensional semiconductor memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12550324-B2
Application number	US-202217570874-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Jul 7, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

First claim

What is claimed is:

1 . A three-dimensional semiconductor memory device, comprising:
a substrate; a stack structure including a plurality of gate electrodes stacked in a vertical direction on the substrate and a plurality of string selection electrodes spaced apart from each other in a horizontal direction on the gate electrodes; a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, the first separation structure including an insulating material; a plurality of vertical channel structures penetrating the stack structure; and a plurality of bit lines having connection with the vertical channel structures and extending in a second direction intersecting the first direction, wherein a first subset of the vertical channel structures is connected in common to one of the bit lines, the vertical channel structures of the first subset being adjacent to each other in the second direction across the first separation structure, wherein each of the string selection electrodes surrounds each of the vertical channel structures of the first subset, and wherein the first separation structure comprises
a first part adjacent to a pair of the vertical channel structures that are adjacent to the first separation structure in the second direction, the first part having a first width in the second direction, the first part having the first width increasing and decreasing in the first direction, both sides of the first part in the second direction having contours inward corresponding to the pair of the vertical channel structures, respectively, each of the contours defining a space in which a portion of a corresponding one of the pair of vertical channel structures is accommodated, and
a second part connected to the first part and having a second width in the second direction, the second width being uniform in the second direction, the first width being equal to or less than the second width in the second direction.

2 . The device of claim 1 , wherein
the first part of the first separation structure is in contact with the string selection electrodes.

3 . The device of claim 1 , wherein the first width in the second direction of the first part repeatedly increases and decreases in the first direction.

4 . The device of claim 1 , wherein
the stack structure comprises a plurality of stack structures, the device further comprises a second separation structure between the stack structures, the second separation structure extending in the first direction, a first top surface of each of the vertical channel structures adjacent to the first separation structure and on a cell array region of the substrate has a first diameter, a second top surface of each of the vertical channel structures adjacent to the second separation structure and on the cell array region of the substrate has a second diameter, and the first diameter is less than the second diameter.

5 . The device of claim 4 , wherein
the second separation structure comprises a plurality of second separation structures, and a second subset of the vertical channel structures is connected in common to one of the bit lines, each of the vertical channel structures of the second subset being adjacent to a corresponding one of the second separation structures.

6 . The device of claim 5 , wherein
each of the second separation structures comprises a protruding part that protrudes toward the vertical channel structures, and each of the vertical channel structures of the second subset comprises a part that protrudes in a same direction in which the protruding part protrudes.

7 . The device of claim 1 , wherein the vertical channel structures are symmetrically arranged with respect to the first separation structure.

8 . The device of claim 7 , wherein a number of the vertical channel structures arranged along the second direction is an even number.

9 . The device of claim 1 , wherein
the stack structure comprises a plurality of stack structures, the device further comprises a plurality of second separation structures between the stack structures, the second separation structures extending in the first direction, the vertical channel structures comprise first to eighth vertical channel structures that are sequentially provided along the second direction, the fourth and fifth vertical channel structures are adjacent to the first separation structure, the first and eighth vertical channel structures are adjacent to corresponding ones of the second separation structures, respectively, the first, third, sixth, and eighth vertical channel structures are aligned with each other in the second direction, and the second, fourth, fifth, and seventh vertical channel structures are aligned with each other in the second direction.

10 . The device of claim 9 , wherein
the bit lines comprise first to fourth bit lines that are arranged along the first direction, and the fourth and fifth vertical channel structures adjacent to the first separation structure are connected in common to the fourth bit line.

11 . The device of claim 10 , wherein
the first and sixth vertical channel structures are connected in common to the first bit line, the third and eighth vertical channel structures are connected in common to the second bit line, and the second and seventh vertical channel structures are connected in common to the third bit line.

12 . The device of claim 10 , wherein the first and eighth vertical channel structures adjacent to corresponding ones of the second separation structures, respectively, are connected in common to the first bit line.

13 . The device of claim 1 , wherein
the stack structure comprises a plurality of stack structures, the device further comprises a second separation structure between the stack structures, the second separation structure extending in the first direction, and a first length in the first direction of the first separation structure is less than a second length in the first direction of the second separation structure.

14 . A three-dimensional semiconductor memory device, comprising:
a substrate; a stack structure including a plurality of gate electrodes stacked in a vertical direction on the substrate and a plurality of string selection electrodes spaced apart from each other in a horizontal direction on the gate electrodes; a source structure between the substrate and the stack structure; a first separation structure between the string selection electrodes and being in a first trench that runs in a first direction across the stack structure; a second separation structure in a second trench on a lateral surface of the stack structure, the second separation structure extending in the first direction; a plurality of vertical channel structures in a plurality of vertical channel holes that penetrate the stack structure, the vertical channel structures being arranged in a zigzag fashion along a second direction intersecting the first direction; a plurality of bit lines connected to the vertical channel structures, the bit lines extending in the second direction; a plurality of bit-line contact plugs connecting the bit lines to corresponding ones of the vertical channel structures, respectively; a dielectric layer covering the stack structure; and a plurality of cell contact plugs penetrating the dielectric layer and at least a portion of the stack structure and connected to either the gate electrodes or the string selection electrodes, wherein a subset of the vertical channel structures is connected in common to one of the bit lines,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaeho
• Kim Jiwon
• Kim Joonsung
• Sung Sukkang
• Lee Sangdon
• Lee Jong-Min
• JUNG Euntaek

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title