Semiconductor storage device and method of manufacturing semiconductor storage device

Patent metadata

Field	Value
Publication number	US-10937803-B2
Application number	US-201916530741-A
Country	US
Kind code	B2
Filing date	Aug 2, 2019
Priority date	Feb 21, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a plurality of first conductor layers stacked in a first direction;
a first semiconductor layer extending in the first direction through the plurality of first conductor layers;
a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer;
a second conductor layer disposed above an uppermost layer of the plurality of first conductor layers;
a second semiconductor layer extending in the first direction through the second conductor layer and electrically connected to the first semiconductor layer;
a third conductor layer disposed between the second semiconductor layer and the second conductor layer, the third conductor layer electrically connected to the second conductor layer;
a first insulator layer disposed above the third conductor layer; and
a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer, and including a second portion disposed between the second semiconductor layer and the first insulator layer, the second insulator layer being a continuous film from at least the first portion to the second portion, wherein
the first portion of the second insulator layer has a first diameter, the second portion of the second insulator layer has a second diameter, and the second diameter is greater than the first diameter.

2. The semiconductor storage device according to claim 1 , wherein
the second semiconductor layer includes a first portion extending along the first portion of the second insulator layer and a second portion extending along the second portion of the second insulator layer, the second semiconductor layer is a continuous film from the first portion of the second semiconductor layer to the second portion of the second semiconductor layer, and wherein a diameter of second portion of the second semiconductor layer is less than a diameter of the first portion of the second semiconductor layer.

3. The semiconductor storage device according to claim 1 , further comprising:
a third insulator layer that divides the second conductor layer into two portions, the third insulator layer and being in contact with the third conductor layer.

4. The semiconductor storage device according to claim 1 , wherein
the second insulator layer includes a second charge storage layer.

5. The semiconductor storage device according to claim 1 , further comprising:
a fourth insulator layer that divides each of the plurality of first conductor layers and the second conductor layer into two portions.

6. A semiconductor storage device comprising:
a stacked body including a plurality of first conductor layers stacked in a first direction;
a first semiconductor layer extending in the first direction through the plurality of first conductor layers;
a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer;
a second conductor layer disposed above the stacked body;
a second semiconductor layer extending in the first direction through the second conductor layer and electrically coupled to the first semiconductor layer;
a third conductor layer disposed between the second semiconductor layer and the second conductor layer, the third conductor layer being electrically coupled to the second conductor layer;
a first insulator layer disposed above the second conductor layer; and
a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer, the second insulator layer being a continuous film from the first portion to the second portion and being in contact with an upper surface of the third conductor layer.

7. The semiconductor storage device according to claim 6 , wherein
a diameter of the second portion of the second insulator layer is less than a diameter of the first portion of the second insulator layer.

8. The semiconductor storage device according to claim 6 , wherein
the second semiconductor layer includes a first portion along the first portion of the second insulator layer and a second portion along the second portion of the second insulator layer, the second semiconductor layer is a continuous film from the first portion of the second semiconductor layer to the second portion of the second semiconductor layer, and wherein a diameter of second portion of the second semiconductor layer is less than a diameter of the first portion of the second semiconductor layer.

9. The semiconductor storage device according to claim 6 , further comprising:
a third insulator layer that divides the second conductor layer into two portions, the third insulator layer being in contact with the third conductor layer and the second insulator layer.

10. The semiconductor storage device according to claim 6 , wherein
the second insulator layer includes a second charge storage layer.

11. The semiconductor storage device according to claim 6 , further comprising:
a fourth insulator layer that divides the plurality of first conductor layers and the second conductor layer into two portions.

12. A method of manufacturing a semiconductor storage device, the method comprising:
forming a stacked body including a plurality of first sacrificial materials stacked in a first direction;
forming a pillar including a first semiconductor layer extending in the first direction through the stacked body and a first charge storage layer disposed between the plurality of first sacrificial materials and the first semiconductor layer;
forming a second sacrificial material above the stacked body, and forming a hole extending through the second sacrificial material in the first direction;
sequentially forming a first conductor layer and a third sacrificial material in the hole, and then removing a portion of the third sacrificial material and a portion of the first conductor layer to expose a side wall of the hole, the removed portion of the third sacrificial material and the removed portion of the first conductor layer extending from an upper end of the hole to a predetermined depth;
forming a first insulator layer along the side wall of the hole to be thicker than the first conductor layer, and then removing a remaining portion of the third sacrificial material; and
removing a portion of the first conductor layer formed at a lower end of the hole.

13. The method according to claim 12 , further comprising:
forming a second insulator layer in the hole after removing the portion of the first conductor layer;
removing a portion of the second insulator layer at the lower end of the hole to expose the first semiconductor layer; and
forming a second semiconductor layer in the hole that exposes the first semiconductor layer.

14. The method according to claim 13 , further comprising:
forming the second semiconductor layer, and then removing the second sacrificial material and forming a second conductor in a part of a region from which the second sacrificial material is removed.

15. The method according to claim 12 , further comprising:
before forming the hole, forming a slit for dividing the second sacrificial material and forming a third insulator layer in the slit, wherein
forming the hole includes exposing the third insulator layer to a sidewall of the hole.

16. The method according to claim 13 , further comprising:
after removing the portion of the first conductor layer and before forming the sec

Assignees

• Toshiba Memory Corp

Inventors

• Kashima Takayuki
• Nyui Kohei
• Fujii Kotaro
• Yamasaki Hiroyuki

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic