Semiconductor memory device having pillars on a peripheral region and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10020319-B2
Application number	US-201615233885-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Jan 27, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A semiconductor memory device includes a plurality of wiring layers formed on a substrate, one or more first pillars penetrating through the wiring layers on a memory region of the substrate and in contact with the substrate, a plurality of memory transistors being formed at portions of each of the one or more first pillars that penetrate the wiring layers, and one or more second pillars penetrating through at least one of the wiring layers on a peripheral region of the substrate and in contact with the substrate. Each of the first and second pillars includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of word-line layers formed above a substrate;
a first select-line layer formed above the word-line layers in a first memory region of the substrate;
a second select-line layer formed above the word-line layers in a second memory region of the substrate;
one or more first pillars penetrating through the first select-line layer and the word-line layers in the first memory region and in contact with the substrate, and one or more second pillars penetrating through the second select-line layer and the word-line layers in the second memory region and in contact with the substrate, a plurality of memory transistors being formed at portions of the first and second pillars that penetrate the word-line layers; and
a partitioning member electrically separating the first select-line layer and the second select-line layer, wherein
each of the first pillars, the second pillars, and the partitioning member includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.

2. The semiconductor memory device according to claim 1 , wherein
a plurality of the first pillars is arranged along a first line extending in a first direction, on the first memory region of the substrate,
a plurality of the second pillars is arranged along the first line, on the second memory region of the substrate, and
the partitioning member extends in a second direction, which crosses the first line.

3. The semiconductor memory device according to claim 1 , wherein
the partitioning member does not penetrate any of the word-line layers.

4. The semiconductor memory device according to claim 1 , wherein
the semiconductor portion of each of the one or more first pillars and each of the one or more second pillars is connected to a bit line, and
the semiconductor portion of the partitioning member is connected to no wiring line.

5. The semiconductor memory device according to claim 1 , further comprising:
one or more third pillars penetrating through at least one of the word-line layers on a peripheral region of the substrate and in contact with the substrate, each of the one or more third pillars includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.

6. The semiconductor memory device according to claim 5 , wherein
a plurality of the first pillars is arranged along a first line extending in a first direction, on the first memory region of the substrate,
a plurality of the second pillars is arranged along the first line, on the second memory region of the substrate, and
a plurality of the third pillars is arranged along a second line that is parallel to the first line, on the peripheral region of the substrate.

7. The semiconductor memory device according to claim 6 , wherein
each of the third pillars is located at end of one of the word-line layers.

8. The semiconductor memory device according to claim 6 , further comprising:
a plurality of contact pillars arranged along the line, each of the contact pillars being formed on an exposed surface of one of the wiring layers and electrically connected to a word line.

9. The semiconductor memory device according to claim 5 , wherein
the semiconductor portion of each of the first pillars is connected to a bit line, and
the semiconductor portion of each of the third pillars is connected to no wiring line.

Assignees

• Toshiba Memory Corp

Inventors

• Baba Yasuyuki

Classifications

• H01L29/792

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic