Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9865615-B2
Application number	US-201615170558-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Jan 8, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction;
a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines; and
a contact plug extending, from one of the channel layers, toward one of the bit lines,
wherein the contact plug includes a first portion being contacted with an inner wall of one of the channel layers and being surrounded by one of the channel layers: and
a second portion extending from the first portion to be contacted with one of the bit lines.

2. The semiconductor device of claim 1 , wherein at least one of the width in the second direction of each of the bit lines and the width in the second direction of the contact plug are formed narrow as compared with the width in the second direction of the uppermost end of one of the channel layers.

3. The semiconductor device of claim 1 , wherein each of the channel layers is formed in a tubular shape surrounding a core insulating layer, and the height of each of the channel layers is formed higher than that of the core insulating layer.

4. The semiconductor device of claim 3 , wherein
the first portion is disposed on the core insulating layer.

5. The semiconductor device of claim 1 , wherein the width in the second direction of the second portion is equal to the width in the second direction of the bit line connected to the contact plug.

6. The semiconductor device of claim 1 , wherein the contact plug includes doped silicon.

7. The semiconductor device of claim 1 , further comprising interlayer dielectric layers and conductive patterns, which are alternately stacked while surrounding the channel layers.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/41741

  Electricity · mapped topic