Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2017200733-A1
Application number	US-201615170558-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Jan 8, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction; a plurality of channel layers disposed under the bit lines the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines; and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

2 . The semiconductor device of claim 1 , wherein at least one of the width in the second direction of each of the bit lines and the width in the second direction of the contact plug are formed narrow a compared with the width in the second direction of the uppermost end of the channel layer.

3 . The semiconductor device of claim 1 , wherein the channel layer is formed in a tubular shape surrounding a core insulating layer, and the height of the channel layer is formed higher than that of the core insulating layer.

4 . The semiconductor device of claim 3 , wherein the contact plug includes:
a first portion disposed on the core insulating layer, the first portion being contacted with an inner wall of the channel layer and being surrounded by the channel layer; and a second portion extending from the first portion to be contacted with one of the bit lines.

5 . The semiconductor device of claim 4 , wherein the width in the second direction of the second portion is equal to the width in the second direction of the bit line connected to the contact plug.

6 . The semiconductor device of claim 1 , wherein the contact plug includes doped silicon.

7 . The semiconductor device of claim 1 , further comprising interlayer dielectric layers and conductive patterns, which are alternately stacked while surrounding the channel layer.

8 . A semiconductor device comprising:
a stack including interlayer dielectric layers and conductive patterns, which are alternately stacked; a channel layer penetrating the stack; an upper insulating layer formed over the stack to cover the channel layer; a bit line disposed in the upper insulating layer while being spaced apart from the channel layer, the bit line being overlapped with a portion of the channel layer; and a contact plug having the same width as the bit line in a width direction perpendicular to the extending direction of the bit line, the contact plug penetrating the upper insulating layer, the contact plug extending toward the bit line from the channel layer.

9 . The semiconductor device of claim 8 , further comprising a source line disposed under the stack.

10 . The semiconductor device of claim 9 wherein the source line includes a first source layer and a second source layer disposed on the first source layer, and
the channel layer extends to the inside of the first source layer by penetrating the second source layer, and is contacted with the second source layer.

11 . The semiconductor device of claim 8 , wherein the diameter of the channel layer in the width direction is greater than that of the contact plug protruding upward of the channel layer.

12 . The semiconductor device of claim 8 , wherein the contact plug protruding upward of the channel layer completely covers the channel layer in the extending direction of the bit line, and covers a portion of the channel layer in the width direction.

13 . The semiconductor device of claim wherein the contact plug includes doped silicon.

14 . The semiconductor device of claim 8 , wherein the contact plug includes a portion extending toward a central area of the channel layer under the upper insulating layer, the portion being surrounded by the channel layer.

15 . A method of manufacturing a semiconductor device, the method comprising:
forming a stack including first material layer and second material layers, which are alternately stacked; forming a channel layer penetrating the stack; forming an upper insulating layer over the stack to cover the channel layer; forming a first mask pattern including a first opening on the upper insulating layer; etching the upper insulating layer by a partial thickness through an etching process using the first mask pattern as an etching barrier, thereby forming a trench partially overlapped with the channel layer in the upper insulating layer; forming, on the first mask pattern, a second mask pattern including a second opening through which a partial area of the trench overlapped with the channel layer is opened; and etching the upper insulating layer exposed in an area in which the first opening and the second opening are overlapped with each other, thereby forming a contact hole through which the channel layer is exposed.

16 . The method of claim 15 , further comprising: after the exposing of the channel layer,
removing the first mask pattern and the second mask pattern; forming a contact plug contacted with the channel layer, the contact plug being filled in the contact hole; and forming a bit line contacted with the contact plug, the bit line being filled in the trench.

17 . The method of claim 16 , wherein the forming of the contact plug is performed through epitaxial growth using the channel layer as a seed layer.

18 . The method of claim 15 , wherein the first mask pattern includes a trench-type mask pattern, and the second mask pattern includes a hole-type mask pattern, and
wherein the channel layer is formed in a tubular shape surrounding a core insulating layer.

19 . The method of claim 18 , further comprising: before the forming of the upper insulating layer,
removing an upper portion of the core insulating layer, thereby lowering the height of the core insulating layer; and filling a capping layer in the area in which the core insulating layer is removed.

20 . The method of claim 19 , further comprising: after the forming of the contact hole,
removing the second mask pattern, the first mask pattern, and the capping layer; forming a contact plug including a first portion contacted with an inner wall of the channel layer while being filled in the area in which the capping layer is removed and a second portion extending from the first portion to be filled in the contact hole; and forming a bit line contacted with the contact plug, the bit line being filled in the trench.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L21/76877

  Electricity · mapped topic