String selection structure of three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-9236340-B2
Application number	US-201314088127-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Jan 11, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
a selection line extending along a first direction;
first and second upper lines horizontally crossing over the selection line and extending along a second direction orthogonal to the first direction; and
first and second vertical patterns vertically crossing the selection line and extending along a third direction orthogonal to the first and second directions, the first and second vertical patterns connected to the first and second upper lines, respectively,
wherein each of the first and second vertical patterns overlaps both of the first and second upper lines, when viewed from plan view.

2. The three-dimensional semiconductor device of claim 1 , wherein the first and second vertical patterns are arranged along a longitudinal direction of the first and second upper lines.

3. The three-dimensional semiconductor device of claim 1 , wherein a width of each of the first and second upper lines is smaller than about half a width of each of the first and second vertical patterns.

4. The three-dimensional semiconductor device of claim 1 , further comprising plugs interposed between the first and second upper lines and the first and second vertical patterns, wherein each of the plugs connects one of the first and second upper lines to a corresponding one of the first and second vertical patterns.

5. The three-dimensional semiconductor device of claim 4 , wherein the first and second vertical patterns constitute a pair of selection transistors sharing the selection line as a gate electrode thereof.

6. The three-dimensional semiconductor device of claim 1 , wherein at least two upper lines including the first and second upper lines are provided on each of the first and second vertical patterns.

7. A three-dimensional semiconductor device, comprising:
first and second selection lines that are stacked one on the other;
an upper line horizontally crossing over the first and second selection lines; and
first and second vertical patterns vertically crossing the first and second selection lines, wherein the first and second vertical patterns are connected in common to the upper line, wherein each of the first and second vertical patterns includes a plurality of memory cells,
wherein an upper portion of each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other, the first and second selection transistors respectively having first and second threshold voltages that are different from each other, and wherein the first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

8. The three-dimensional semiconductor device of claim 7 , wherein the first selection transistors of the first and second vertical patterns, respectively, use the first and second selection lines as their respective gate electrodes, and wherein the second selection transistors of the first and second vertical patterns, respectively, use the second and first selection lines as their respective gate electrodes.

9. The three-dimensional semiconductor device of claim 7 , further comprising: an additional upper line horizontally crossing over the first and second selection lines; and a third vertical pattern vertically crossing the first and second selection lines, the third vertical pattern connected to the additional upper line, wherein each of the first, second, and third vertical patterns overlaps both of the upper line and the additional upper line, when viewed in plan view.

10. The three-dimensional semiconductor device of claim 7 , wherein both of the first and second selection transistors include metal-oxide-semiconductor field effect transistors (MOSFETs) of substantially the same conductivity type, and wherein the first threshold voltage is lower than the second threshold voltage.

11. The three-dimensional semiconductor device of claim 7 , wherein both of the first and second selection transistors include n-MOSFETs, and wherein the first threshold voltage is a negative value, and the second threshold voltage is a positive value.

12. The three-dimensional semiconductor device of claim 7 , wherein the first and second selection transistors comprise a charge storing layer, and wherein the first selection transistors are subjected to electrical erasing to have a threshold voltage lower than a threshold voltage of the second selection transistors.

13. The three-dimensional semiconductor device of claim 7 , wherein the first selection transistors of the first and second vertical patterns include n-MOSFETs, and wherein at least one of the n-MOSFETs has an n-type channel region.

14. A three-dimensional semiconductor device, comprising:
unit structures, at least one of the unit structures including:
first and second selection lines stacked one on the other; and
first and second vertical patterns penetrating the first and second selection lines; and
upper lines provided on the unit structures, the upper lines crossing over the first and second selection lines,
wherein in the at least one of the unit structures, the first and second vertical patterns are connected in common to one of the upper lines,
wherein each of the first and second vertical patterns includes a plurality of memory cells, and an upper portion of each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other,
wherein the first and second selection transistors, respectively, have first and second threshold voltages that are different from each other, and
wherein the first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

15. The three-dimensional semiconductor device of claim 14 , wherein the unit structures comprise first and second unit structures adjacent to each other, the first and second unit structures having substantially mirror symmetry.

16. The three-dimensional semiconductor device of claim 15 , wherein the first and second unit structures are spaced apart from each other.

17. The three-dimensional semiconductor device of claim 15 , wherein the first and second unit structures at least partially contact each other.

18. The three-dimensional semiconductor device of claim 15 , wherein the second vertical pattern of the first unit structure functions as the second vertical pattern of the second unit structure.

19. The three-dimensional semiconductor device of claim 18 , wherein an upper portion of the second vertical pattern is at least partially cut by a slit that is formed substantially parallel to the upper line.

20. The three-dimensional semiconductor device of claim 15 , wherein each of the first and second unit structures further comprises plugs disposed between the first and second vertical patterns and the upper lines, and wherein the plugs of the first and second unit structures have substantially mirror symmetry.

21. The three-dimensional semiconductor device of claim 15 , wherein each of the first and second unit structures further comprises plugs disposed between the first and second vertical patterns and the upper lines, and wherein the plugs of the first and second unit structures have substantially rotational symmetry.

22. The three-dimensional semiconductor device of claim 15 , wherein each of the first and second unit structures further co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Hwang Sung-Min

Classifications

• G11C11/5635 Primary

  Erasing circuits · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title