Vertical memory devices and methods of manufacturing vertical memory devices

Patent metadata

Field	Value
Publication number	US-10373972-B2
Application number	US-201815943861-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Oct 11, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a cell array including a plurality of cell regions spaced apart from each other in a second direction, each cell region of the plurality of cell regions including a regularly arranged plurality of vertical channels;
a plurality of bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and
a plurality of bit-line contacts respectively electrically connecting the plurality of vertical channels and the plurality of bit-lines,
wherein each cell region of the plurality of cell regions includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction,
wherein the plurality of vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each of the cell regions, and
wherein the plurality of bit-line contacts are configured to electrically connect each bit-line of the plurality bit-lines to at least two vertical channels having different types.

2. The vertical memory device as claimed in claim 1 , wherein:
the vertical channels are disposed to form a zigzag arrangement along the first direction, and
the zigzag arrangement is repeated in the second direction.

3. The vertical memory device as claimed in claim 2 , wherein:
each cell region of the plurality of cell regions further includes at least one dummy channel, and
the plurality of vertical channels and the at least one dummy channel are disposed to form the zigzag arrangement.

4. The vertical memory device as claimed in claim 3 , wherein the at least one dummy channel is provided in the sub isolation region of each cell region of the plurality of cell regions.

5. The vertical memory device as claimed in claim 3 , wherein the at least one dummy channel has a same configuration as a configuration of each vertical channel of the plurality vertical channels.

6. The vertical memory device as claimed in claim 1 , wherein:
the cell array further includes at least one isolation region, the at least one isolation region extending in the first direction and being configured to electrically isolate each cell region of the plurality of cell regions in the second direction,
the plurality of cell regions includes:
a first cell region isolated by a first isolation region and a second isolation region; and
a second cell region isolated by the second isolation region and a third isolation region,

the first cell region includes a first sub isolation region configured to isolate the first cell region in the second direction, and
the second cell region includes a second sub isolation region configured to isolate the second cell region in the second direction.

7. The vertical memory device as claimed in claim 6 , wherein:
first vertical channels of the plurality of vertical channels are provided on the first cell region and arranged to have an axial symmetry with respect to the first sub isolation region;
second vertical channels of the plurality of vertical channels are provided on the second cell region and arranged to have an axial symmetry with respect to the second sub isolation region;
the first vertical channels and the second vertical channels are arranged to have an axial symmetry with respect to the second isolation region, and
at least one first dummy channel is provided on the first cell region and at least one second dummy channel is provided on the second cell region and are arranged to have an axial symmetry with respect to the second isolation region.

8. The vertical memory device as claimed in claim 7 , wherein:
the at least one first dummy channel is provided on the first sub isolation region;
the at least one second dummy channel is provided on the second sub isolation region;
first bit-line contacts of the plurality of bit-line contacts are provided on the first cell region and on an imaginary line parallel to the second direction, and are arranged to have a point symmetry with respect to the first sub isolation region;
second bit-line contacts of the plurality of bit-line contacts are provided on the second cell region and on the imaginary line, and are arranged to have a point symmetry with respect to the second sub isolation region; and
the first bit-line contacts and the second bit-line contacts are arranged to have a point symmetry with respect to the second isolation region.

9. The vertical memory device as claimed in claim 8 , wherein:
the first cell region further includes a first dummy contact formed on the at least one first dummy channel; and
the second cell region further includes a second dummy contact formed on the at least one second dummy channel.

10. The vertical memory device as claimed in claim 7 , wherein:
the at least one first dummy channel is provided on the first sub isolation region;
the at least one second dummy channel is provided on the second sub isolation region;
first bit-line contacts of the plurality of bit-line contacts are provided on the first cell region and on an imaginary line parallel to the second direction, and are arranged to have a point symmetry with respect to the first sub isolation region;
second bit-line contacts of the plurality of bit-line contacts are provided on the second cell region and are arranged to have an axial symmetry with respect to the second sub isolation region; and
the first bit-line contacts and the second bit-line contacts on the imaginary line are arranged to have a point symmetry with respect to the second isolation region.

11. The vertical memory device as claimed in claim 10 , wherein:
the first cell region further includes a first dummy contact formed on the at least one first dummy channel; and
the second cell region further includes a second dummy contact formed on the at least one second dummy channel.

12. The vertical memory device as claimed in claim 6 , wherein:
first vertical channels of the plurality of vertical channels are provided on the first cell region and are arranged to have an axial symmetry with respect to the first sub isolation region;
second vertical channels of the plurality of vertical channels are provided on the second cell region and are arranged to have an axial symmetry with respect to the second sub isolation region;
the first vertical channels and the second vertical channels are on imaginary line parallel to the second direction and are arranged to have an axial symmetry with respect to the second isolation region, and
at least one first dummy channel is provided on the first cell region and at least a second dummy channel is provided on the second cell region and are arranged to have a point symmetry with respect to the second isolation region and the imaginary line.

13. The vertical memory device as claimed in claim 12 , wherein:
the at least one first dummy channel is provided on the first sub isolation region;
the at least one second dummy channel is provided on the second sub isolation region;
first bit-line contacts of the plurality of bit-line contacts are provided on the first cell region and on the imaginary line, and are arranged to have a point symmetry with respect to the first sub isolation region;
second bit-line contacts of the plurality of bit-line contacts are provided on the second cell region and on the imaginary line, and are arranged to have a point symmetry with respect to the second sub isolation region; and
the first bit-line contacts and the second bit-line contacts are arranged to have a point sy

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park An-Soo
• Kim Sung-Hoon
• Kwak Pan-Suk

Classifications

• G11C16/0466 Primary

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title