High selectivity etching with germanium-containing gases

Patent metadata

Field	Value
Publication number	US-12520558-B2
Application number	US-202418656033-A
Country	US
Kind code	B2
Filing date	May 6, 2024
Priority date	Jul 16, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

First claim

What is claimed is:

1 . A method, comprising:
forming a first semiconductor layer and a second semiconductor layer on a substrate, wherein the first semiconductor layer comprises germanium; etching through the first and second semiconductor layers to form an opening; delivering a primary etchant and a germanium-containing gas to the second semiconductor layer through the opening; and etching an end portion of the second semiconductor layer with the primary etchant and the germanium-containing gas.

2 . The method of claim 1 , wherein forming the first semiconductor layer comprises epitaxially growing the first semiconductor layer with silicon.

3 . The method of claim 1 , wherein forming the second semiconductor layer comprises epitaxially growing the second semiconductor layer with silicon germanium having germanium in a range from about 40 atomic percent to about 100 atomic percent.

4 . The method of claim 1 , wherein delivering the primary etchant and the germanium-containing gas comprises delivering the germanium-containing gas to the second semiconductor layer at a flow rate ranging from about 0.1 to about 3000 sccm.

5 . The method of claim 1 , wherein delivering the primary etchant and the germanium-containing gas comprises:
delivering the primary etchant at a first flow rate; and delivering the germanium-containing gas at a second flow rate, a ratio of the second flow rate to the first flow rate ranges from about 0.1 to about 100.

6 . The method of claim 1 , wherein etching the end portion of the second semiconductor layer comprises:
etching the end portion of the second semiconductor layer with the primary etchant at a first etch rate; and etching the end portion of the second semiconductor layer with the germanium-containing gas at a second etch rate, wherein a ratio of the first etch rate to the second etch rate ranges from about 1 to about 500.

7 . The method of claim 1 , further comprising etching the first semiconductor layer with the primary etchant, wherein an etch selectivity between the second semiconductor layer and the first semiconductor layer ranges from about 20 to about 100.

8 . The method of claim 1 , wherein the germanium-containing gas comprises one of germanium hydride, germanium fluoride, germanium chloride, and germanium hydrofluoride.

9 . The method of claim 1 , wherein the primary etchant comprises at least one of a hydrogen radical, a fluorine radical, a nitrogen fluoride radical, fluorine, hydrogen fluoride, carbon fluoride, chlorine, and hydrogen chloride.

10 . A method, comprising:
forming a stack of semiconductor layers on a substrate, wherein the stack of semiconductor layers comprises first semiconductor layers and second semiconductor layers stacked in an alternating configuration; etching the stacked of semiconductor layers to form an opening; delivering a primary etchant and a germanium-containing gas through the opening to the second semiconductor layers; etching a first portion of the second semiconductor layers in the opening with the primary etchant and the germanium-containing gas; forming an inner spacer structure at the first portion; and etching a second portion of the second semiconductor layers adjacent to the inner spacer structure with the primary etchant and the germanium-containing gas.

11 . The method of claim 10 , further comprising forming a gate structure at the second portion of the second semiconductor layers, wherein the gate structure wraps around the first semiconductor layers.

12 . The method of claim 10 , wherein forming the stack of semiconductor layers comprises epitaxially growing the second semiconductor layers with silicon germanium having germanium in a range from about 40 atomic percent to about 100 atomic percent.

13 . The method of claim 10 , wherein delivering the primary etchant and the germanium-containing gas comprises:
delivering the primary etchant at a first flow rate; and delivering the germanium-containing gas at a second flow rate, a ratio of the second flow rate to the first flow rate ranges from about 0.1 to about 100.

14 . The method of claim 10 , wherein etching the first portion of the second semiconductor layers comprises:
etching the first portion of the second semiconductor layers with the primary etchant at a first etch rate; and etching the first portion of the second semiconductor layers with the germanium-containing gas at a second etch rate, wherein a ratio of the first etch rate to the second etch rate ranges from about 1 to about 500.

15 . The method of claim 10 , further comprising etching an end portion of the first semiconductor layers with the primary etchant, wherein an etch selectivity between the second semiconductor layers to the first semiconductor layers ranges from about 20 to about 100.

16 . The method of claim 10 , wherein the germanium-containing gas comprises one of germanium hydride, germanium fluoride, germanium chloride, and germanium hydrofluoride.

17 . A semiconductor device, comprising:
an epitaxial layer on a substrate; a stack of semiconductor layers in contact with a top surface of the epitaxial layer; an epitaxial region on the top surface of the epitaxial layer and in contact with end portions of the stack of semiconductor layers; a gate structure wrapped around a portion of the stack of semiconductor layers; and an inner spacer structure between the gate structure and the epitaxial region, wherein the inner spacer structure comprises:
a first height adjacent to the gate structure,
a second height adjacent to the epitaxial region, and
a width between the gate structure and the epitaxial region,
a ratio of a difference between the first height and the second height to the width being less than about 0.3.

18 . The semiconductor device of claim 17 , wherein:
the stack of semiconductor layers comprises an additional portion in contact with the inner spacer structure; the portion of the stack of semiconductor layers wrapped around by the gate structure comprises a first thickness; the additional portion in contact with the inner spacer structures comprises a second thickness; and a ratio of the second thickness to the first thickness ranges from about 10% to about 100%.

19 . The semiconductor device of claim 17 , wherein:
the stack of semiconductor layers comprises an additional portion in contact with the inner spacer structure; the portion of the stack of semiconductor layers wrapped around by the gate structure has a first thickness; and the additional portion has a second thickness substantially equal to the first thickness.

20 . The semiconductor device of claim 17 , wherein the stack of semiconductor layers comprises germanium in a range from about 40 atomic percent to about 100 atomic percent.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tze-Chung
• Lin Han-Yu
• Lin Pinyen
• Lee Fang-Wei
• Lin Li-Te

Classifications

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title