Method for fabricating a semiconductor device including etching nanostructures

Patent metadata

Field	Value
Publication number	US-12513952-B2
Application number	US-202217689644-A
Country	US
Kind code	B2
Filing date	Mar 8, 2022
Priority date	Jul 22, 2021
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F 2 ) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

First claim

What is claimed is:

1 . A method, comprising:
forming a fin structure on a substrate, the fin structure comprising one or more nanostructures; removing a portion of the fin structure to expose an end of the one or more nanostructures; etching a portion of the end of the one or more nanostructures with one or more etching cycles, each etching cycle comprising:
removing a portion of a native oxide of the nanostructure with an etching process;
removing a remaining portion of the native oxide by purging the fin structure with hydrogen fluoride (HF);
etching the end of the one or more nanostructures with a gas mixture of fluorine (F 2 ) and HF; and
removing an exhaust gas mixture comprising an etching byproduct;
in response to the etched portion of the end of the one or more nanostructures being below a predetermined threshold, performing the one or more etching cycles until a desired etched portion of the end of the one or more nanostructures is reached; and forming an inner spacer in the etched end of the one or more nanostructures.

2 . The method of claim 1 , wherein etching the end of the one or more nanostructures with the one or more etching cycles comprises performing a non-plasma etching process.

3 . The method of claim 1 , wherein a ratio between F 2 and HF in the gas mixture is between about 0.02 and about 0.6.

4 . The method of claim 1 , wherein etching the end of the one or more nanostructures with the one or more etching cycles comprises setting a pressure in an etching chamber performing the one or more etching cycles between about 0.2 Torr and about 0.6 Torr.

5 . The method of claim 1 , wherein etching the end of the one or more nanostructures with the gas mixture comprises flowing F 2 between about 50 sccm and 150 sccm and flowing HF of the gas mixture between about 10 sccm and about 70 sccm.

6 . The method of claim 1 , wherein a first nanostructure of the one or more nanostructures is above a second nanostructure of the one or more nanostructures, and wherein etching the end of the one or more nanostructures with the one or more etching cycles comprises etching a different amount of a first end of the first nanostructure from a second end of the second nanostructure.

7 . The method of claim 1 , further comprising:
forming an other fin structure comprising one or more other nanostructures on the substrate, wherein a spacing between the fin structure and an adjacent fin structure is smaller than an other spacing between the other fin structure and an other adjacent fin structure; and etching an end of the one or more other nanostructures with the one or more etching cycles, wherein an etched amount of the end of the one or more other nanostructures is different than that of the one or more nanostructures.

8 . The method of claim 1 , wherein removing the exhaust gas mixture comprises reducing a pressure in an etching chamber performing the one or more etching cycles by a vacuum pump.

9 . The method of claim 1 , further comprising:
etching a middle portion of the one or more nanostructures with the one or more etching cycles; and forming a gate region in the etched middle portion of the one or more nanostructures.

10 . The method of claim 1 , further comprising:
forming a gate structure over the fin structure, comprising:
depositing an interfacial oxide (IO) layer;
depositing a high-k (HK) gate dielectric layer on the IO layer;
depositing a work function metal (WFM) layer on the HK gate dielectric layer; and
depositing a gate metal fill layer on the WFM layer;
forming a spacer on the gate structure; and forming a source/drain (S/D) region in the removed portion of the fin structure and adjacent to the gate structure.

11 . A method, comprising:
forming a fin structure on a substrate, the fin structure comprising one or more nanostructures; etching a portion of an end of the one or more nanostructures with one or more etching cycles, each etching cycle comprising:
removing a portion of a native oxide of the nanostructure with an etching process;
removing a remaining portion of the native oxide by purging the fin structure with hydrogen fluoride (HF); and
etching the end of the one or more nanostructures with a gas mixture of fluorine (F 2 ) and HF;
in response to the etched portion of the end of the one or more nanostructures being below a predetermined threshold, performing the one or more etching cycles until a desired etched portion of the end of the one or more nanostructures is reached; forming an inner spacer in the etched end of the one or more nanostructures; etching a middle portion of the one or more nanostructures with the one or more etching cycles; and forming a gate region in the etched middle portion of the one or more nanostructures.

12 . The method of claim 11 , wherein etching the end of the one or more nanostructures with the one or more etching cycles comprises performing a non-plasma etching process.

13 . The method of claim 11 , wherein a ratio between F 2 and HF in the gas mixture is between about 0.02 and about 0.6.

14 . The method of claim 11 , wherein etching the end of the one or more nanostructures with the one or more etching cycles comprises setting a pressure in an etching chamber performing the one or more etching cycles between about 0.2 Torr and about 0.6 Torr.

15 . The method of claim 11 , further comprising removing an exhaust gas mixture comprising an etching byproduct, wherein removing the exhaust mixture comprises removing one or more of silicon tetrafluoride (SiF 4 ), germanium tetrafluoride (GeF 4 ), silicon trifluoride (SiF 3 ), germanium trifluoride (GeF 3 ), silicon difluoride (SiF 2 and SiHF 2 ), difluorosilane (SiH 2 F 2 ), germanium difluoride (GeF 2 and GeHF 2 ), difluorogermane (GeH 2 F 2 ), silicon fluoride (SiH 2 F and SiHF), fluorosilane (SiH 3 F), germanium fluoride (GeH 2 F and GeHF), fluorogermane (GeH 3 F), and combinations thereof.

16 . The method of claim 11 , wherein the fin structure further comprises one or more nanostructured channel layers above, below, and interposed between the one or more nanostructures, and wherein the method further comprises:
forming a shallow trench isolation (STI) region at a bottom portion of the fin structure; forming a gate structure over the fin structure; forming a spacer on the gate structure; forming a source/drain (S/D) region on a portion of the fin structure and adjacent to the gate structure; and forming an etch stop layer (ESL) and an interlayer dielectric (ILD) layer on the S/D region and on a sidewall of the spacer.

17 . A method, comprising:
forming a fin structure on a substrate, the fin structure comprising one or more nanostructures; removing a portion of the fin structure to expose an end of the one or more nanostructures; and etching a portion of the end of the one or more nanostructures with one or more etching cycles, each etching cycle comprising:
removing a portion of an oxide of the nanostructure with an etching process;
removing a remaining portion of the oxide by purging the fin structure with hydrogen fluoride (HF);
etching the end of the one or more nanostructures with a gas mixture of fluorine (F 2 ) and HF; and
in response to the etched portion of the end of the one or more nanostructures being below a predetermined threshold, performing the one or more etching cycles until a desired etched portion of the end of the one or more nanostructures is reached.

18 . The method of claim 17 , wherein etching the end of the one or more nanost

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconducor Mfg Company Ltd

Inventors

• Kuang Chia-Chien
• Chen Wei-Lun
• Lin Tze-Chung
• Lin Li-Te

Classifications

• H10P50/246

  of Group III-V materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title