Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer

US12477798B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12477798-B2
Application numberUS-202418428972-A
CountryUS
Kind codeB2
Filing dateJan 31, 2024
Priority dateApr 21, 2021
Publication dateNov 18, 2025
Grant dateNov 18, 2025

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28 ; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28 ; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

First claim

Opening claim text (preview).

That which is claimed is: 1 . A semiconductor device comprising: a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent; a second single crystal silicon layer having a second percentage of silicon 28 greater than 95 percent; at least one quantum bit device associated with the second single crystal silicon layer; and a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. 2 . The semiconductor device of claim 1 , wherein the at least one quantum bit device comprises an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer. 3 . The semiconductor device of claim 1 , wherein the non-semiconductor monolayer comprises oxygen. 4 . The semiconductor device of claim 1 , wherein the superlattice is between the first and second single crystal silicon layers. 5 . The semiconductor device of claim 1 , wherein the second percentage of silicon 28 is greater than 99 percent. 6 . A semiconductor device comprising: a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent; a second single crystal silicon layer having a second percentage of silicon 28 greater than 99 percent; at least one quantum bit device associated with the second single crystal silicon layer; and a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. 7 . The semiconductor device of claim 6 , wherein the at least one quantum bit device comprises an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer. 8 . The semiconductor device of claim 6 , wherein the superlattice is between the first and second single crystal silicon layers.

Assignees

Inventors

Classifications

  • having composition variations in the channel regions · CPC title

  • Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

  • Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects · CPC title

  • being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

  • of IGFETs · CPC title

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What does patent US12477798B2 cover?
A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28 ; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28 ; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group o…
Who is the assignee on this patent?
Atomera Inc
What technology area does this patent fall under?
Primary CPC classification H10D62/8164. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).