Semiconductor device including threshold voltage measurement circuitry
US-10107854-B2 · Oct 23, 2018 · US
US12477798B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12477798-B2 |
| Application number | US-202418428972-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 31, 2024 |
| Priority date | Apr 21, 2021 |
| Publication date | Nov 18, 2025 |
| Grant date | Nov 18, 2025 |
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A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28 ; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28 ; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.
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That which is claimed is: 1 . A semiconductor device comprising: a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent; a second single crystal silicon layer having a second percentage of silicon 28 greater than 95 percent; at least one quantum bit device associated with the second single crystal silicon layer; and a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. 2 . The semiconductor device of claim 1 , wherein the at least one quantum bit device comprises an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer. 3 . The semiconductor device of claim 1 , wherein the non-semiconductor monolayer comprises oxygen. 4 . The semiconductor device of claim 1 , wherein the superlattice is between the first and second single crystal silicon layers. 5 . The semiconductor device of claim 1 , wherein the second percentage of silicon 28 is greater than 99 percent. 6 . A semiconductor device comprising: a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent; a second single crystal silicon layer having a second percentage of silicon 28 greater than 99 percent; at least one quantum bit device associated with the second single crystal silicon layer; and a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. 7 . The semiconductor device of claim 6 , wherein the at least one quantum bit device comprises an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer. 8 . The semiconductor device of claim 6 , wherein the superlattice is between the first and second single crystal silicon layers.
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