Self-aligned scheme for semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-12476146-B2
Application number	US-202318365490-A
Country	US
Kind code	B2
Filing date	Aug 4, 2023
Priority date	Mar 31, 2021
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

First claim

What is claimed is:

1 . A device comprising:
a first conductive feature and a second conductive feature embedded in a first insulating layer, the first conductive feature being a first distance from the second conductive feature; a low-k dielectric layer disposed over the first insulating layer; a high-k dielectric layer disposed over the low-k dielectric layer; a second insulating layer disposed over the high-k dielectric layer; and a third conductive feature embedded in the second insulating layer and physically contacting the first conductive feature, the high-k dielectric layer being directly interposed between a first portion and a second portion of the third conductive feature, the first portion of the third conductive feature being a second distance from the second conductive feature, the second distance being less than the first distance.

2 . The device of claim 1 , wherein the second portion of the third conductive feature is a third distance from the second conductive feature, the third distance being less than the first distance.

3 . The device of claim 2 , wherein the second portion is interposed between the first insulating layer and the high-k dielectric layer.

4 . The device of claim 1 , wherein the third conductive feature further physically contacts sidewalls of the low-k dielectric layer, the high-k dielectric layer, and the second insulating layer.

5 . The device of claim 4 , wherein the third conductive feature further physically contacts a top surface of the high-k dielectric layer.

6 . The device of claim 1 , wherein the high-k dielectric layer being directly interposed between the first portion and the second portion of the third conductive feature comprises:
the first portion being in physical contact with an upper surface of the high-k dielectric layer; and the second portion being in physical contact with a lower surface of the high-k dielectric layer, the lower surface being opposite to the upper surface.

7 . The device of claim 1 , wherein the first conductive feature comprises a cobalt capping layer, and wherein a sidewall of the cobalt capping layer is in physical contact with a sidewall of the low-k dielectric layer.

8 . The device of claim 1 , wherein the low-k dielectric layer comprises a first segment extending between the third conductive feature and the second conductive feature, wherein the high-k dielectric layer comprises a second segment extending between the third conductive feature and the second conductive feature, and wherein the first segment is shorter than the second segment.

9 . A device comprising:
a first conductive feature embedded in a first inter-metal dielectric (IMD) layer; a low-k dielectric layer disposed over the first IMD layer; a high-k dielectric layer disposed over the low-k dielectric layer; an etch stop layer disposed over and physically contacting the first conductive feature and the high-k dielectric layer; a second IMD layer disposed over the etch stop layer; and a second conductive feature embedded in the second IMD layer and physically contacting the first conductive feature, the high-k dielectric layer, the etch stop layer, and the second IMD layer, the second conductive feature comprising an underbite portion interposed between the high-k dielectric layer and the first IMD layer.

10 . The device of claim 9 , wherein the second conductive feature further physically contacts the low-k dielectric layer.

11 . The device of claim 9 , wherein the second conductive feature comprises an overbite portion directly above the high-k dielectric layer and the first IMD layer.

12 . The device of claim 9 further comprising a third conductive feature embedded in the first IMD layer and laterally displaced from the first conductive feature.

13 . The device of claim 12 , wherein the third conductive feature is closer to the second conductive feature than to the first conductive feature.

14 . The device of claim 9 , wherein the first conductive feature comprises a cobalt capping layer, and wherein a sidewall of the cobalt capping layer physically contacts a sidewall of the low-k dielectric layer.

15 . A device comprising:
a first extra-low-k dielectric layer over a substrate; a first conductive feature and a second conductive feature embedded in the first extra-low-k dielectric layer, the first extra-low-k dielectric layer comprising a first segment extending from the first conductive feature to the second conductive feature; a low-k dielectric layer over the first extra-low-k dielectric layer, the low-k dielectric layer comprising a second segment extending along a top surface of the first segment and between the first conductive feature and the second conductive feature; a high-k dielectric layer over the low-k dielectric layer, the high-k dielectric layer comprising a third segment extending along a top surface of the second segment and between the first conductive feature and the second conductive feature; an etch stop layer over the high-k dielectric layer, the etch stop layer comprising a fourth segment extending along a top surface of the third segment, a sidewall of the third segment, and a sidewall of the second segment; a second extra-low-k dielectric layer over the high-k dielectric layer; and a third conductive feature embedded in the second extra-low-k dielectric layer and in physical contact with the first conductive feature.

16 . The device of claim 15 , wherein the fourth segment of the etch stop layer is in physical contact with the third conductive feature and the second conductive feature.

17 . The device of claim 15 , wherein the third segment is longer than the second segment.

18 . The device of claim 15 , wherein the third conductive feature comprises a first portion in physical contact with the second segment and the third segment, and wherein the first portion is directly interposed between the second segment and the third segment.

19 . The device of claim 18 , wherein the first portion of the third conductive feature is closer to the second conductive feature than the first conductive feature is to the second conductive feature.

20 . The device of claim 9 , wherein in a cross-section a first segment of the low-k dielectric layer extends along the first IMD layer between the first conductive feature and the second conductive feature, wherein in the cross-section a second segment of the high-k dielectric layer extends along the first segment, wherein an upper surface of the first segment is in contact with a lower surface of the second segment, and wherein the lower surface of the second segment is longer than the upper surface of the first segment.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu cai-ling
• Hsueh Hsiu-Wen
• Wang Wei-Ren
• Huang Po-Hsiang
• Chen Chii-Ping
• Wang Jen Hung

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title