Self-aligned hard masks with converted liners

Patent metadata

Field	Value
Publication number	US-10937689-B2
Application number	US-201616465510-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

In one embodiment, a trench may be formed in a dielectric surface, and the trenched may be lined with a liner. The trench may be filled with a metal, and the metal may be recessed below an opening of the trench. The liner may be converted into a dielectric, and a hard mask may be deposited into the trench.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of interconnect layers, wherein the plurality of interconnect layers comprises a first interconnect layer and a second interconnect layer, wherein the first interconnect layer comprises a first interconnect, and wherein the second interconnect layer comprises a second interconnect; and
a via connecting the first interconnect and the second interconnect;
wherein the apparatus includes a trench in a first dielectric material, the trench includes a lower region including the first interconnect, the trench includes an upper region, the first interconnect includes a first line, the upper region includes a second liner, the first liner is in contact with the second liner, the first liner is a conductive material, the second liner is a second dielectric material, and the second dielectric material has a different material composition than the first dielectric material.

2. The apparatus of claim 1 , wherein the second dielectric material comprises a metal element or a semiconductor element.

3. The apparatus of claim 1 , wherein the second dielectric material further comprises nitrogen and oxygen.

4. The apparatus of claim 1 , wherein the via extends into the upper region of the trench.

5. The apparatus of claim 1 , wherein the upper region of the trench includes a hardmask material, and the hardmask material has a different material composition than the second liner.

6. The apparatus of claim 5 , wherein at least a portion of the hardmask material is spaced apart from side walls of the trench by the second liner.

7. The apparatus of claim 5 , wherein a portion of the via contacts the hardmask material.

8. The apparatus of claim 1 , wherein a lower portion of the via is spaced apart from side walls of the trench by the second liner.

9. The apparatus of claim 1 , wherein a central vertical axis of the via is not aligned with a central vertical axis of the trench.

10. A method, comprising:
forming a trench in a dielectric surface;
lining the trench with a liner;
filling the trench with a metal;
recessing the metal below an opening of the trench;
converting the liner into a dielectric; and
depositing a hard mask into the trench.

11. The method of claim 10 , further comprising forming a via using the hard mask to align the via.

12. The method of claim 10 , wherein converting the liner into the dielectric comprises exposing the liner to an oxidizing plasma.

13. The method of claim 10 , wherein the liner is converted into an oxide, a silicate, or an oxynitride.

14. A computing device, comprising:
a circuit board; and
an integrated circuit disposed on the circuit board, wherein the integrated circuit comprises:
a plurality of interconnect layers, wherein the plurality of interconnect layers comprises a first interconnect layer and a second interconnect layer, wherein the first interconnect layer comprises a first interconnect, and wherein the second interconnect layer comprises a second interconnect; and
a via connecting the first interconnect and the second interconnect;
wherein the via extends into an upper portion of a trench, the first interconnect is in a lower portion of the trench, the lower portion of the trench includes a conductive liner material, and the upper portion of the trench includes a dielectric liner material.

15. The computing device of claim 14 , wherein the dielectric liner material comprises a metal element.

16. The computing device of claim 14 , wherein the upper portion of the trench includes a hardmask material, and the hardmask material has a different material composition than the dielectric liner material.

17. The computing device of claim 16 , wherein at least a portion of the hardmask material is spaced apart from side walls of the trench by the dielectric liner material.

18. The computing device of claim 16 , wherein a portion of the via is adjacent to the hardmask material.

19. The computing device of claim 14 , wherein a lower portion of the via is spaced apart from side walls of the trench by the dielectric liner material.

20. The computing device of claim 14 , wherein the conductive liner material contacts the dielectric liner material.

Assignees

• Intel Corp

Inventors

• Chandhok Manish
• Suri Satyarth
• Tronic Tristan A
• Jezewski Christopher J
• Schenker Richard E

Classifications

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/065

  by making at least a portion of the conductive part non-conductive, e.g. by oxidation · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title