Semiconductor device including a superlattice providing metal work function tuning

Patent metadata

Field	Value
Publication number	US-12439658-B2
Application number	US-202217663852-A
Country	US
Kind code	B2
Filing date	May 18, 2022
Priority date	May 18, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

First claim

The invention claimed is:

1. A semiconductor gate-all-around (GAA) device comprising:
a semiconductor substrate;
source and drain regions on the semiconductor substrate;
a plurality of semiconductor nanostructures extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 wherein the dopant diffusion liner comprises respective portions adjacent each of the source and drain regions.

3. The semiconductor device of claim 1 further comprising a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

4. The semiconductor device of claim 1 further comprising a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

5. The semiconductor device of claim 1 further comprising a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

6. The semiconductor device of claim 1 further comprising a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

7. The semiconductor device of claim 1 wherein the gate comprises a metal.

8. The semiconductor device of claim 1 wherein the base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

10. A semiconductor gate-all-around (GAA) device comprising:
a semiconductor substrate;
source and drain regions on the semiconductor substrate;
a plurality of semiconductor nanostructures extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement;
source and drain dopant diffusion liners adjacent respective portions of the source and drain regions and each comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

11. The semiconductor device of claim 10 further comprising a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

12. The semiconductor device of claim 10 further comprising a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

13. The semiconductor device of claim 10 further comprising a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

14. The semiconductor device of claim 10 wherein the gate comprises a metal.

15. A semiconductor gate-all-around (GAA) device comprising:
a semiconductor substrate;
source and drain regions on the semiconductor substrate;
a plurality of semiconductor nanostructures extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

16. The semiconductor device of claim 15 wherein the dopant diffusion liner comprises respective portions adjacent each of the source and drain regions.

17. The semiconductor device of claim 15 further comprising a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

18. The semiconductor device of claim 15 further comprising a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

19

Assignees

• Atomera Inc

Inventors

• Mears Robert J
• Takeuchi Hideki

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3246

  Monolayers · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title