Semiconductor devices with enhanced deterministic doping and related methods

Patent metadata

Field	Value
Publication number	US-9716147-B2
Application number	US-201514734412-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Jun 9, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a plurality of stacked groups of layers on a semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region; and
performing a rapid thermal anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

2. The method of claim 1 wherein selectively implanting comprises using a focused ion beam.

3. The method of claim 2 further comprising selecting a depth of the focused ion beam to a depth of the plurality of stacked groups of layers.

4. The method of claim 1 wherein the at least one localized region comprises a plurality thereof.

5. The method of claim 1 wherein the dopant has a fall-off in a range of 3.0 to 3.3 nm/decade.

6. The method of claim 1 wherein forming the plurality of stacked groups of layers comprises forming laterally-spaced apart stacked groups of layers on the semiconductor substrate; and wherein implanting comprises implanting the dopant in respective localized regions beneath each of the laterally-spaced apart stacked groups of layers.

7. The method of claim 1 wherein the dopant comprises at least one of boron and arsenic.

8. The method of claim 1 wherein each base semiconductor portion comprises silicon.

9. The method of claim 1 wherein each base semiconductor portion comprises germanium.

10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

11. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

12. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

13. A method for making a semiconductor device comprising:
forming a plurality of stacked groups of layers on a semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region; and
performing a rapid thermal anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region with the dopant being isolated from the plurality of stacked groups of layers by portions of the semiconductor substrate therebetween.

14. The method of claim 13 wherein selectively implanting comprises using a focused ion beam.

15. The method of claim 14 further comprising selecting a depth of the focused ion beam to a depth of the plurality of stacked groups of layers.

16. The method of claim 13 wherein the at least one localized region comprises a plurality thereof.

17. The method of claim 13 wherein the dopant has a fall-off in a range of 3.0 to 3.3 nm/decade.

18. The method of claim 13 wherein forming the plurality of stacked groups of layers comprises forming laterally-spaced apart stacked groups of layers on the semiconductor substrate; and wherein implanting comprises implanting the dopant in respective localized regions beneath each of the laterally-spaced apart stacked groups of layers.

19. The method of claim 13 wherein the dopant comprises at least one of boron and arsenic.

20. The method of claim 13 wherein each base semiconductor portion comprises silicon.

21. The method of claim 13 wherein each base semiconductor portion comprises germanium.

Assignees

• Atomera Inc

Inventors

• Mears Robert J

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title