Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice

Patent metadata

Field	Value
Publication number	US-12417912-B2
Application number	US-202418669156-A
Country	US
Kind code	B2
Filing date	May 20, 2024
Priority date	Mar 3, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

First claim

The invention claimed is:

1. A semiconductor integrated circuit (IC) comprising:
a semiconductor-on-insulator substrate comprising an insulator layer and a doped semiconductor layer thereon, the doped semiconductor layer having a first region and a second region adjacent thereto;
a superlattice over the first and second adjacent regions of the semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the first region of the semiconductor layer comprising a first dopant concentration to serve as a Radio Frequency (RF) ground plane layer for a first semiconductor RF device; and
the second region of the semiconductor layer comprising a second dopant concentration for a threshold voltage adjustment of a second semiconductor device;
wherein the doped semiconductor layer of the semiconductor-on-insulator substrate has a thickness of 35 nm or less.

2. The semiconductor IC of claim 1 comprising:
respective first and second body regions above the superlattice;
respective source and drain regions associated with the first and second body regions; and
respective first and second gates associated with the first and second body regions.

3. The semiconductor IC of claim 2 comprising a first body contact coupled to the first body region.

4. The semiconductor IC of claim 1 wherein the first semiconductor RF device comprises an RF switch.

5. The semiconductor IC of claim 1 wherein the RF ground plane layer has a thickness in a range of 10-50 nm.

6. The semiconductor IC of claim 1 wherein the base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

7. The semiconductor IC of claim 1 wherein the base semiconductor monolayers comprise silicon.

8. The semiconductor IC of claim 1 wherein the non-semiconductor monolayers comprise oxygen.

9. The semiconductor IC of claim 1 wherein the semiconductor-on-insulator substrate comprises a silicon-on-insulator (SOI) substrate.

10. A semiconductor integrated circuit (IC) comprising:
a semiconductor-on-insulator substrate comprising an insulator layer and a doped semiconductor layer thereon, the doped semiconductor layer having a first region and a second region adjacent thereto;
a superlattice over the first and second adjacent regions of the semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the first region of the semiconductor layer and adjacent portions of the superlattice comprising a first dopant concentration to serve as a Radio Frequency (RF) ground plane layer for a first semiconductor RF device; and
the second region of the semiconductor layer and adjacent portions of the superlattice comprising a second dopant concentration for a threshold voltage adjustment of a second semiconductor device;
wherein the doped semiconductor layer of the semiconductor-on-insulator substrate has a thickness of 35 nm or less.

11. The semiconductor IC of claim 10 comprising:
respective first and second body regions above the superlattice;
respective source and drain regions associated with the first and second body regions; and
respective first and second gates associated with the first and second body regions.

12. The semiconductor IC of claim 11 comprising a first body contact coupled to the first body region.

13. The semiconductor IC of claim 10 wherein the first semiconductor RF device comprises an RF switch.

14. The semiconductor IC of claim 10 wherein the RF ground plane layer has a thickness in a range of 10-50 nm.

15. The semiconductor IC of claim 10 wherein the base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

16. The semiconductor IC of claim 10 wherein the base semiconductor monolayers comprise silicon.

17. The semiconductor IC of claim 10 wherein the non-semiconductor monolayers comprise oxygen.

18. The semiconductor IC of claim 10 wherein the semiconductor-on-insulator substrate comprises a silicon-on-insulator (SOI) substrate.

19. A semiconductor integrated circuit (IC) comprising:
a silicon-on-insulator substrate comprising an insulator layer and a doped silicon layer thereon, the doped silicon layer having a first region and a second region adjacent thereto;
a superlattice over the first and second adjacent regions of the semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
the first region of the silicon layer comprising a first dopant concentration to serve as a Radio Frequency (RF) ground plane layer for a first semiconductor RF device; and
the second region of the silicon layer comprising a second dopant concentration for a threshold voltage adjustment of a second semiconductor device;
wherein the doped semiconductor layer of the semiconductor-on-insulator substrate has a thickness of 35 nm or less.

20. The semiconductor IC of claim 19 comprising:
respective first and second body regions above the superlattice;
respective source and drain regions associated with the first and second body regions; and
respective first and second gates associated with the first and second body regions.

21. The semiconductor IC of claim 19 wherein the first semiconductor RF device comprises an RF switch.

22. The semiconductor IC of claim 19 wherein the RF ground plane layer has a thickness in a range of 10-50 nm.

23. The semiconductor IC of claim 19 wherein the base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

Assignees

• Atomera Inc

Inventors

• Takeuchi Hideki
• Mears Robert J

Classifications

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10D62/8164

  comprising only semiconductor materials  (potential variation in long-range structurally-disordered materials H10D62/8163) · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title