Flexible merge scheme for source/drain epitaxy regions

Patent metadata

Field	Value
Publication number	US-12408315-B2
Application number	US-202318517275-A
Country	US
Kind code	B2
Filing date	Nov 22, 2023
Priority date	Apr 20, 2017
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

First claim

What is claimed is:

1. A method comprising:
depositing a spacer layer comprising first portions on first semiconductor fins, and second portions on second semiconductor fins;
forming first fin spacers on opposing sides of the first semiconductor fins;
forming second fin spacers on opposing sides of the second semiconductor fins, wherein the second fin spacers are taller than the first fin spacers; and
performing an epitaxy process to simultaneously grow first epitaxy semiconductor regions based on the first semiconductor fins and second epitaxy semiconductor regions based on the second semiconductor fins, wherein when the first epitaxy semiconductor regions grown from neighboring ones of the first semiconductor fins start to merge with each other, the second epitaxy semiconductor regions grown from neighboring ones of the second semiconductor fins are separated from each other.

2. The method of claim 1 , wherein at a time when the epitaxy process is finished, the second epitaxy semiconductor regions grown from neighboring ones of the second semiconductor fins are separated from each other.

3. The method of claim 1 , wherein the forming the first fin spacers comprises performing a first etching process on a first spacer layer, and the forming the second fin spacers comprises performing a second etching process on a second spacer layer.

4. The method of claim 3 , wherein the first etching process and the second etching process are separate etching processes.

5. The method of claim 4 , wherein the first etching process lasts longer than the second etching process.

6. The method of claim 1 , wherein the first fin spacers have a first height, and the second fin spacers have a second height greater than the first height.

7. The method of claim 6 , wherein the second height of the second fin spacers is greater than about 1 . 5 times the first height of the first fin spacers.

8. The method of claim 1 , wherein neighboring fins in the first semiconductor fins have a first distance, and neighboring fins in the second semiconductor fins have a second distance equal to the first distance.

9. The method of claim 1 , wherein neighboring fins in the first semiconductor fins have a first distance, and neighboring fins in the second semiconductor fins have a second distance smaller than the first distance.

10. The method of claim 1 , wherein the first semiconductor fins overlap first semiconductor strips that are in first isolation regions, and the second semiconductor fins overlap second semiconductor strips that are in second isolation regions, and wherein the method further comprises:
etching the first semiconductor fins to form first recesses between the first fin spacers, wherein the first epitaxy semiconductor regions are grown from the first recesses; and
etching the second semiconductor fins to form second recesses between the second fin spacers, wherein the second epitaxy semiconductor regions are grown from the second recesses.

11. A method comprising:
forming first fin spacers on opposing sides of a first semiconductor strip and a second semiconductor strip;
forming second fin spacers on opposing sides of a third semiconductor strip and a fourth semiconductor strip, wherein the second fin spacers are taller than the first fin spacers; and
forming first epitaxy semiconductor regions from the first semiconductor strip and the second semiconductor strip, wherein the first epitaxy semiconductor regions are merged with each other; and
forming second epitaxy semiconductor regions from the third semiconductor strip and the fourth semiconductor strip, and the second epitaxy semiconductor regions are separated from each other when the forming the second epitaxy semiconductor regions is ended.

12. The method of claim 11 , wherein the first semiconductor strip and the second semiconductor strip have a first distance from each other, and wherein the third semiconductor strip and the fourth semiconductor strip have a second distance from each other, with the second distance being equal to or smaller than the first distance.

13. The method of claim 12 , wherein the second distance is smaller than the first distance.

14. The method of claim 11 , wherein the first epitaxy semiconductor regions and the second semiconductor epitaxy regions are comprised in a first Fin Field-Effect Transistor (FinFET) and a second FinFET, respectively.

15. The method of claim 11 , wherein the first epitaxy semiconductor regions and the second epitaxy semiconductor regions are epitaxially grown in a same epitaxy process.

16. The method of claim 11 further comprising depositing a dielectric layer on tops and opposing sides of the first, the second, the third, and the fourth semiconductor strips, wherein: the forming the first fin spacers and the forming the second fin spacers comprise a first etching process for forming the first fin spacers, and a second etching process for forming the second fin spacers.

17. The method of claim 16 , wherein the first etching process and the second etching process are performed at different times.

18. The method of claim 16 , wherein the first fin spacers and the second fin spacers are formed in separate lithography processes using separate photoresists.

19. A method comprising:
forming first fin spacers on sidewalls of first semiconductor fins;
forming second fin spacers on sidewalls of second semiconductor fins, wherein a first spacing between two immediate neighboring ones of the first semiconductor fins is greater than a second spacing between two immediate neighboring ones of the second semiconductor fins, and wherein the first fin spacers have a first height, and the second fin spacers have a second height different from the first height;
recessing the first semiconductor fins;
recessing the second semiconductor fins; and
in a common epitaxy process, growing first epitaxy semiconductor regions from the recessed first semiconductor fins and second epitaxy semiconductor regions from the recessed second semiconductor fins.

20. The method of claim 19 , wherein at a time the common epitaxy process is ended, the first epitaxy semiconductor regions merge with each other, and the second epitaxy semiconductor regions are separate from each other.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yu Chia-Ta
• Yang Cheng-Yu
• Wang Sheng-Chen
• Yeong Sai-Hooi
• Yang Feng-Cheng
• Chen Yen-Ming

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D84/853

  comprising FinFETs · CPC title