Structure and method for semiconductor device

Patent metadata

Field	Value
Publication number	US-9287382-B1
Application number	US-201414535005-A
Country	US
Kind code	B1
Filing date	Nov 6, 2014
Priority date	Nov 6, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate with first and second device regions, wherein the first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions;
etching a plurality of first recesses in the first S/D region and a plurality of second recesses in the second S/D regions;
growing a first plurality of first epitaxial features in the first recesses and a second plurality of first epitaxial features in the second recesses; and
growing a third plurality of second epitaxial features over the first plurality and a fourth plurality of second epitaxial features over the second plurality, wherein the third plurality merge into a merged second epitaxial feature and the fourth plurality separate from each other.

2. The method of claim 1 , further comprising:
growing a third epitaxial feature over the merged second epitaxial feature while keeping the fourth plurality separate from each other.

3. The method of claim 2 , wherein each of the first, second, and third epitaxial features includes SiGe.

4. The method of claim 3 , wherein the first, second, and third epitaxial features have a Ge-to-Si ratio in a range from about 10% to about 80%.

5. The method of claim 3 , wherein the first, second, and third epitaxial features are in-situ doped with boron with a dopant concentration in a range from about 2×e 20 cm −3 to about 3×e 21 cm 3 .

6. The method of claim 3 , wherein the first, second, and third epitaxial features include SiGe formed by cyclic deposition and etching (CDE) processes.

7. The method of claim 6 , wherein the CDE process forming the first epitaxial features uses a deposition gas mixture of about 1% to about 10% GeH 4 in H 2 , an etching gas of HCl, and a ratio of a flow rate of the deposition gas mixture to a flow rate of the etching gas is about 2.5 to about 10.

8. The method of claim 7 , wherein the flow rate of the deposition gas mixture is about 100 to about 1000 standard cubic centimeters per minute (sccm) and the flow rate of the etching gas is about 50 to about 1000 sccm.

9. The method of claim 6 , wherein the CDE process forming the third epitaxial feature uses a deposition gas mixture of about 1% to about 10% GeH 4 in H 2 , an etching gas of HCl, and a ratio of a flow rate of the deposition gas mixture to a flow rate of the etching gas is about 2.5 to about 10.

10. The method of claim 2 , wherein the semiconductor substrate is a silicon substrate and the merged second epitaxial feature provides a top surface in (100) silicon crystal plane.

11. The method of claim 1 , wherein the plurality of first recesses includes at least three recesses.

12. The method of claim 1 , wherein the first device region is for forming logic field-effect transistor (FET) devices and the second device region is for forming SRAM FET devices.

13. A method of forming a FinFET device, comprising:
providing a silicon substrate with a first device region and a second device region, wherein the first device region includes a first silicon fin and the second device region includes a plurality of second silicon fins;
etching a plurality of first recesses in an S/D region of the first silicon fin and a plurality of second recesses in S/D regions of the second silicon fins;
growing a first plurality of first epitaxial features in the first recesses and a second plurality of first epitaxial features in the second recesses;
growing a third plurality of second epitaxial features over the first plurality and a fourth plurality of second epitaxial features over the second plurality, wherein the third plurality merge into a merged second epitaxial feature and the fourth plurality separate from each other; and
growing a third epitaxial feature over the merged second epitaxial feature, while keeping the fourth plurality separate from each other.

14. The method of claim 13 , wherein the first, second, and third epitaxial features include SiGe for forming raised S/D features for p-type devices.

15. The method of claim 13 , wherein the first, second, and third epitaxial features include Si for forming raised S/D features for n-type devices.

16. The method of claim 13 , wherein the first device region is for logic FinFET devices and the second device region is for SRAM FinFET devices.

17. A semiconductor device, comprising:
a substrate having a first device region and a second device region, wherein the first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions;
a plurality of first recesses in the first S/D region;
a first epitaxial feature having bottom portions and a top portion over the bottom portions, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region;
a plurality of second recesses, one in each of the second S/D regions; and
a plurality of second epitaxial features each having a bottom portion in one of the second recesses, wherein the second epitaxial features separate from each other.

18. The semiconductor device of claim 17 , wherein the first and second epitaxial features include SiGe.

19. The semiconductor device of claim 17 , wherein the first epitaxial feature is a raised S/D feature for a logic field-effect transistor (FET) device and the second epitaxial features each are a raised S/D feature for a memory FET device.

20. The semiconductor device of claim 17 , wherein the substrate is a silicon substrate and the first and second S/D regions are formed in silicon fins of the substrate.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lee Yi-Jing
• Li Kun-Mu
• Li Chii-Horng
• Lee Tze-Liang

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D86/215

  comprising FinFETs · CPC title