Semiconductor device and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12396174-B2
Application number	US-202217968058-A
Country	US
Kind code	B2
Filing date	Oct 18, 2022
Priority date	Oct 22, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a stack structure including a gate stack region and a dummy stack region, the gate stack region including interlayer insulating layers and gate electrodes alternately stacked, and the dummy stack region including dummy insulating layers and dummy horizontal layers alternately stacked;
a separation structure penetrating through the stack structure, surrounding an entire external side surface of the gate stack region, and having a shape of a closed loop;
a vertical memory structure penetrating through the gate stack region in a first region; and
gate contact structures electrically connected to the gate electrodes in a second region adjacent to the first region, wherein:
the gate electrodes include a first gate electrode and a second gate electrode disposed at a level higher than a level of the first gate electrode,
each of the gate contact structures includes a gate contact plug and a first insulating spacer surrounding a side surface of the gate contact plug,
the gate contact plugs include a first gate contact plug and a second gate contact plug,
the first gate contact plug penetrates through the second gate electrode, and contacts the first gate electrode, and
the second gate contact plug is at a higher level than the first gate electrode, and contacts the second gate electrode.

2. The semiconductor device of claim 1 , further comprising a dummy structure, including:
a hole penetrating through at least a portion of the dummy stack region;
a liner covering a sidewall and a bottom of the hole;
a second insulating spacer between the liner and the sidewall of the hole; and
a gap-fill layer filling the hole, and disposed on the liner,
wherein a width of the dummy structure is greater than a width of each of the gate contact structures.

3. The semiconductor device of claim 2 , wherein the liner includes a same material as a material of the gate contact plugs.

4. The semiconductor device of claim 1 , further comprising etch stop detection regions, wherein:
the etch stop detection regions include dummy structures penetrating through the dummy stack region,
each of the dummy structures includes:
an etch stop detection hole penetrating through the dummy stack region;
a liner covering a sidewall and a bottom of the etch stop detection hole; and
a gap-fill layer filling the etch stop detection hole, and disposed on the liner, and

at least one of the etch stop detection regions has a maximum width greater than a width of a first word line among the gate electrodes.

5. The semiconductor device of claim 1 , wherein an entire external side surface of the first gate electrode and an entire external side surface of the second gate electrode are in contact with the separation structure.

6. The semiconductor device of claim 1 , wherein:
the gate electrodes include lower select gate electrodes disposed on the same plane, word lines vertically stacked and spaced apart from each other on the lower select gate electrodes, and upper select gate electrodes disposed on the same plane on the word lines,
the word lines include the first and second gate electrodes,
each of the word lines extends in a first direction perpendicular to a vertical direction,
the lower select gate electrodes are spaced apart from each other in a second direction perpendicular to the first direction, and
the upper select gate electrodes are spaced apart from each other in the second direction.

7. The semiconductor device of claim 6 , wherein a total number of the upper select gate electrodes is greater than a total number of the lower select gate electrodes.

8. The semiconductor device of claim 6 , wherein the gate electrodes further include a lower erase control gate electrode disposed below the lower select gate electrodes, and upper erase control gate electrodes on the upper select gate electrodes.

9. The semiconductor device of claim 1 , further comprising:
a peripheral circuit structure; and
a plate pattern on the peripheral circuit structure, wherein:
the peripheral circuit structure includes:
a semiconductor substrate;
peripheral circuits and a peripheral circuit wiring on the semiconductor substrate; and
a lower insulating structure covering the peripheral circuits and the peripheral circuit wiring, and disposed on the semiconductor substrate,

the plate pattern includes at least one silicon layer, and
the gate stack region is disposed on the plate pattern.

10. The semiconductor device of claim 9 , further comprising:
through contact structures penetrating through the dummy stack region, and disposed on an external side of the separation structure; and
gate connection wirings electrically connecting the through contact structures to the gate contact structures, and disposed on a level higher than a level of the stack structure.

11. The semiconductor device of claim 9 , further comprising:
through contact structures surrounded by the separation structure and penetrating through the gate stack region; and
gate connection wirings electrically connecting the through contact structures to the gate contact structures, and disposed on a level higher than a level of the stack structure,
wherein each of the through contact structures includes a through contact plug and a second insulating spacer on a side surface of the through contact plug.

12. The semiconductor device of claim 1 , wherein:
the first gate contact plug includes a first portion and a second portion disposed on the first portion, and
a central axis between both side surfaces of the first portion is misaligned with a central axis between both side surfaces of the second portion.

13. The semiconductor device of claim 1 , further comprising:
a plate pattern; and
a peripheral circuit structure, wherein:
the peripheral circuit structure includes:
a semiconductor substrate;
peripheral circuits and peripheral circuit wiring disposed below the semiconductor substrate; and
an insulating structure covering the peripheral circuits and the peripheral circuit wiring, and below the semiconductor substrate, and

the stack structure is disposed between the plate pattern and the peripheral circuit structure.

14. The semiconductor device of claim 1 , wherein:
the stack structure includes a lower stack structure and an upper stack structure disposed on the lower stack structure,
the lower stack structure includes lower interlayer insulating layers and lower gate electrodes alternately stacked,
the upper stack structure includes upper interlayer insulating layers and upper gate electrodes alternately stacked, and
the vertical memory structure includes a slope changing portion in which a slope of a side surface changes between an uppermost electrode among the lower gate electrodes and a lowermost electrode among the upper gate electrodes.

15. A semiconductor device, comprising:
memory mats, each of the memory mats including memory blocks;
a dummy stack region surrounding the memory mats; and
a block separation structure having a shape of a closed loop surrounding a side surface of each of the memory blocks, wherein:
each of the memory blocks has a memory cell array region and a gate connection region disposed on at least one side of the memory cell array region,
each of the memory blocks includes a gate stack region including gate electrodes stacked and spaced apart from each other in a vertical direction, vertical memory structures penetrating through the gate stack region in the memory cell array region, and gate contact structures in contact with the gate electrodes in the g

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Junhyoung
• Lee Seungmin
• Han Sangbeom
• Lim Joonsung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/40

  characterised by the peripheral circuit region · CPC title