Semiconductor devices including word line interconnecting structures

Patent metadata

Field	Value
Publication number	US-9337207-B2
Application number	US-201414191542-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Apr 11, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate including a cell region and an interconnection region;
adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region;
layers of word lines stacked on the substrate, each layer including a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, the word lines including respective word line pads extending into the interconnection region;
an isolation pattern separating the first and second word lines in the cell region and the interconnection region; and
contact plugs disposed on opposite sides of the isolation pattern in the interconnection region and contacting the word line pads,
wherein each of the contact plugs comprises a first conductive pattern penetrating at least one of the word line pads and electrically connecting with one word pad disposed below the at least one of the word line pads and a second conductive pattern extending vertically from the one word line pad and surrounding the first conductive pattern.

2. The semiconductor memory device of claim 1 , further comprising respective first and second string selection lines disposed on respective ones of the first word lines and the second word lines.

3. The semiconductor memory device of claim 2 , further comprising respective ground selection lines underlying the first and second word lines.

4. The semiconductor memory device of claim 1 , wherein sidewalls of the word line pads are substantially vertically aligned with each other.

5. The semiconductor memory device of claim 1 , wherein heights of bottom surfaces of the plugs decrease with distance from the cell region.

6. The semiconductor memory device of claim 1 , wherein a height difference between adjacent ones of the plugs adjacent is substantially equal to a height difference between the word line pads connected thereto.

7. The semiconductor memory device of claim 1 , wherein the first conductive pattern and the second conductive pattern include the same material layer as the word lines.

8. The semiconductor memory device of claim 1 , wherein each of the plugs further includes an insulating spacer surrounding the second conductive pattern.

9. The semiconductor memory device of claim 8 , wherein each insulating spacer separates the associated plug from at least one of the word line pads.

10. The semiconductor memory device of claim 1 , wherein a thickness of the word lines is less than a width of the plugs.

11. The semiconductor memory device of claim 1 , wherein the first conductive pattern and the second conductive pattern comprise respective different materials.

12. The semiconductor memory device of claim 1 , further comprising a gate insulating layer disposed between the vertical channels and the word lines and extending on upper and lower surfaces of the word lines.

Assignees

• Park Jintaek
• Park Youngwoo
• Lee Jaeduk
• Samsung Electronics Co Ltd

Inventors

• Park Jintaek
• Park Youngwoo
• Lee Jaeduk

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic