Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9577085-B2
Application number	US-201414496026-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Jun 3, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths.

First claim

What is claimed is:

1. A semiconductor device, comprising:
interlayer insulating layers stacked in a first direction and separated from each other;
word lines formed between the interlayer insulating layers;
sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed; and
cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a lower sidewall of the first pillar portion to surround the lower sidewall of the first pillar portion and contacting a sidewall of one of the word lines, the first protruding portion having a bottom surface or a top surface facing one of the sacrificial insulating layers,
wherein the cell contact plugs have different depths.

2. The semiconductor device of claim 1 , further comprising a spacer insulating layer surrounding the first pillar portion.

3. The semiconductor device of claim 1 , further comprising:
two or more selection lines stacked over the interlayer insulating layers and separated from each other; and
a select contact plug including a second pillar portion extending in the first direction and two or more second protruding portions protruding from a sidewall of the second pillar portion and contacting sidewalls of the selection lines.

4. The semiconductor device of claim 3 , further comprising:
dummy conductive patterns separated from the selection lines and formed at the layers where the selection lines are formed; and
a dummy contact plug including a third pillar portion extending in the first direction and a third protruding portion protruding from a sidewall of the third pillar portion and contacting a sidewall of a lowermost dummy conductive pattern, among the dummy conductive patterns.

5. The semiconductor device of claim 4 , further comprising a buried insulating layer formed between the selection lines and the dummy conductive patterns.

6. The semiconductor device of claim 1 , further comprising:
two or more selection lines stacked over the interlayer insulating layers and separated from each other; and
select contact plugs each including a second pillar portion extending in the first direction and a second protruding portion extending from a sidewall of the second pillar portion and contacting a sidewall of one of the selection lines, wherein the select contact plugs have different depths.

7. The semiconductor device of claim 6 , further comprising a spacer insulating layer surrounding the second pillar portion.

8. The semiconductor device of claim 1 , wherein the cell contact plugs are arranged in a matrix format including a plurality of rows and a plurality of columns.

9. The semiconductor device of claim 8 , wherein the cell contact plugs are sequentially arranged with a first depth difference in a row direction of the matrix format and with a second depth difference greater than the first depth difference in a column direction of the matrix format.

10. The semiconductor device of claim 1 , further comprising:
a peripheral transistor arranged under the sacrificial insulating layers and the interlayer insulating layers and including a source region, a drain region, and a gate; and
peripheral contact plugs passing through the sacrificial insulating layers and the interlayer insulating layers and coupled to the source region, the drain region, and the gate of the peripheral transistor.

11. The semiconductor device of claim 10 , further comprising spacer insulating layers surrounding the peripheral contact plugs.

12. The semiconductor device of claim 10 , wherein each of the peripheral contact plugs includes a top portion extending in the first direction to be higher than the word lines, and
the semiconductor device further comprises first buried insulating layers each surrounding the top portion of each of the peripheral contact plugs.

13. A semiconductor device, comprising:
interlayer insulating layers stacked in a first direction and separated from each other;
conductive regions formed between the interlayer insulating layers;
sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the conductive regions are formed; and
cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting one of the conductive regions, the first protruding portion having a bottom surface or a top surface facing one of the sacrificial insulating layers,
wherein at least two contact plugs have different depths.

14. The semiconductor device of claim 13 , wherein at least two contact plugs have the same depth.

15. The semiconductor device of claim 14 , wherein the two contact plugs having the same depth are separated by a first buried insulating layer having the same depth as the two contact plugs having the same depth.

16. The semiconductor device of claim 15 , wherein one of the two contact plugs having the same depth includes a second protruding portion protruding from a sidewall of the first pillar portion and contacting one of the conductive regions different from the conductive region that the first protruding portion contacts.

17. The semiconductor device of claim 16 , wherein the second protruding portion is located at a shallower depth than the first protruding portion.

18. The semiconductor device of claim 13 , wherein the conductive patterns include a selection line, a dummy pattern, or a word line.

19. The semiconductor device of claim 18 , wherein the first protruding portions, that contact conductive regions of a layer including the word line, are located at different depths.

20. The semiconductor device of claim 1 , wherein the cell contact plugs are lined up in a row.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L27/11548

  Electricity · mapped topic