Semiconductor device

Patent metadata

Field	Value
Publication number	US-11437396-B2
Application number	US-202017032128-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Mar 26, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower structure;
a first upper structure including lower gate layers on the lower structure;
a second upper structure including upper gate layers on the first upper structure;
separation structures penetrating the first and second upper structures on the lower structure;
a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and
a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers, wherein:
the memory vertical structure includes a lateral surface having at least one bent portion,
the first contact plug includes a lateral surface having at least one bent portion, and
the at least one bent portion of the lateral surface of the memory vertical structure and the at least one bent portion of the lateral surface of the first contact plug are disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

2. The semiconductor device of claim 1 , wherein:
each of the separation structures has a lateral surface having at least one bent portion, and
the at least one bent portion of the lateral surface of each of the separation structures is disposed between the first height level on which an uppermost gate layer of the lower gate layers is disposed and the second height level on which a lowermost gate layer of the upper gate layers is disposed.

3. The semiconductor device of claim 2 , wherein the separation structures, the memory vertical structure, and the first contact plug have upper surfaces coplanar with one another.

4. The semiconductor device of claim 1 , wherein a lower surface of the first contact plug is at a higher level than a lower surface of the memory vertical structure.

5. The semiconductor device of claim 1 , wherein:
each of the separation structures includes an insulating material layer in contact with the lower and upper gate layers,
the memory vertical structure includes a channel layer, and a data storage structure disposed between the channel layer and the lower and upper gate layers, and
the first contact plug includes a plug gap-fill layer, and a plug barrier layer covering a bottom surface and a lateral surface of the plug gap-fill layer.

6. The semiconductor device of claim 1 , wherein the lower structure includes:
a substrate;
a circuit structure including lower pads on the substrate;
a lower insulating layer covering the circuit structure; and
a pattern structure and an intermediate insulating layer on the lower insulating layer.

7. The semiconductor device of claim 6 , further comprising:
a contact pattern in contact with the pattern structure and in contact with one or a plurality of first lower pads of the lower pads, wherein the contact pattern includes:
a contact gap-fill layer;
a contact barrier layer covering a lateral surface and a bottom surface of the contact gap-fill layer; and
a metal-semiconductor compound layer disposed between the contact barrier layer and the pattern structure.

8. The semiconductor device of claim 7 , further comprising:
a pad pattern spaced apart from the pattern structure and in contact with the first contact plug, wherein:
the contact pattern includes:
a contact portion overlapping the pattern structure and in contact with the pattern structure;
an extension portion extending from the contact portion into the intermediate insulating layer; and
one or a plurality of via portions extending downwardly from the extension portion and in contact with the one or the plurality of first lower pads of the lower pads,

the pad pattern includes:
a pad portion in the intermediate insulating layer; and
a via portion extending downwardly from the pad portion and in contact with a second lower pad of the lower pads,

the contact pattern and the pad pattern have upper surfaces coplanar with each other,
the contact portion of the contact pattern has a first thickness,
both of at least a portion of the extension portion and at least a portion of the pad portion have a second thickness, and
the second thickness is greater than the first thickness.

9. The semiconductor device of claim 8 , wherein:
the contact pattern further includes a lower protrusion extending downwardly from the extension portion, and
the lower protrusion is adjacent to a lateral surface of the pattern structure and is spaced apart from the one or the plurality of via portions.

10. The semiconductor device of claim 6 , further comprising:
a second pad pattern; and
second contact plugs on the second pad pattern, wherein:
at least a portion of the second pad pattern is disposed on a level the same as a level of at least a portion of the pattern structure,
at least one of the second contact plugs includes a lateral surface having at least one bent portion, and
the second pad pattern is in contact with the second contact plugs.

11. The semiconductor device of claim 6 , further comprising: a dummy pattern spaced apart from the pattern structure, wherein: the pattern structure includes a lower pattern layer, an upper pattern layer, and an intermediate pattern layer interposed between the lower pattern layer and the upper pattern layer, a portion of the upper pattern layer is in contact with the lower pattern layer, the dummy pattern includes a lower dummy layer, a dummy intermediate layer, and a dummy upper layer stacked in order, the lower dummy layer has a material and a thickness the same as those of the lower pattern layer, the dummy upper layer has a material and a thickness the same as those of the upper pattern layer, and the dummy intermediate layer includes a material different from a material of the intermediate pattern layer.

12. The semiconductor device of claim 1 , wherein:
the memory vertical structure and the first contact plug have upper surfaces coplanar with each other, and
an upper surface of each of the separation structures is disposed on a level higher than a level of an upper surface of the first contact plug.

13. The semiconductor device of claim 1 , wherein: the memory vertical structure and the first contact plug have upper surfaces coplanar with each other, an upper surface of each of the separation structures is disposed on a level higher than a level of an upper surface of the memory vertical structure, and a lower surface of the first contact plug is disposed on a level higher than a level of a lower surface of the memory vertical structure.

14. The semiconductor device of claim 1 , further comprising:
first gate contact plugs in contact with lower gate pads of the lower gate layers; and
second gate contact plugs in contact with upper gate pads of the upper gate layers, wherein:
the first and second gate contact plugs have upper surfaces disposed on a level higher than a level of an upper surface of the memory vertical structure, and
the first and second gate contact plugs have upper surfaces coplanar with an upper surface of the first contact plug.

15. The semiconductor device of claim 1 , wherein:
the lower structure includes:
a substrate;
a circuit structure including lower pads on the substrate;
a lower insulating layer covering the circuit structure; and
a pattern structure and an intermediate insulating layer on the lower insulating layer,

the first contact plug further includes a pad pattern portion extending downwardly,
a portion of the first contact plug disposed on the pad pa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Junhyoung
• Cheon Jisung
• Son Yoonhwan
• Lee Seungmin

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L27/11578 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic