Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9431336-B2
Application number	US-201213598569-A
Country	US
Kind code	B2
Filing date	Aug 29, 2012
Priority date	Jun 22, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a memory cell region and a contact region;
a stacked structure comprising conductive layers and first interlayer insulating layers alternately stacked over the substrate, wherein the conductive layers and the first interlayer insulating layers extend from the memory cell region to the contact region;
barrier rib patterns including mask layer patterns, spaced apart from one another, provided over the stacked structure in the contact region;
spaces passing through at least one of the conductive layers and the first interlayer insulating layers between the mask layer patterns, wherein the spaces are formed to open the conductive layers, respectively; and
contact plugs and insulating layers alternately filled in the spaces, wherein a length of each of the contact plugs and the insulating layers increases as a distance of each of the contact plugs and the insulating layers from the memory cell region increases.

2. The semiconductor device of claim 1 , wherein the spaces divide the stacked structure formed in the contact region into the barrier rib patterns.

3. The semiconductor device of claim 1 , wherein each of the mask layer patterns includes a first mask layer and a second mask layer over the first mask layer.

4. The semiconductor device of claim 3 , wherein the first mask layer includes insulating material having a different etch selectivity from the conductive layers and the first interlayer insulating layers.

5. The semiconductor device of claim 1 , further comprising a thin insulating layer formed between the contact plugs and the barrier rib patterns.

6. The semiconductor device of claim 1 , wherein the barrier rib patterns are arranged at a uniform interval.

Assignees

• Lim Yong Hyun
• Sk Hynix Inc

Inventors

• Lim Yong Hyun

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/086

  involving buried masks · CPC title