Semiconductor memory

Patent metadata

Field	Value
Publication number	US-10199387-B2
Application number	US-201816104843-A
Country	US
Kind code	B2
Filing date	Aug 17, 2018
Priority date	Mar 13, 2014
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

First claim

What is claimed is:

1. A memory comprising:
a semiconductor substrate;
a first memory cell array above the semiconductor substrate;
a second memory cell array above the semiconductor substrate;
a first interconnection above the semiconductor substrate, the first interconnection facing one side of the first memory cell array;
a second interconnection above the semiconductor substrate, the second interconnection facing the other side of the first memory cell array and one side of the second memory cell array, the second interconnection being electrically connected to the first interconnection; and
a third interconnection extending above the first interconnection, the first memory cell array, the second interconnection and the second memory cell array, the third interconnection being electrically connected to at least one memory cell of the first memory cell array and to at least one memory cell of the second memory cell array.

2. The memory according to claim 1 , wherein
the first interconnection faces the one side of the first memory cell array via a gap, and
the second interconnection faces the other side of the first memory cell array and the one side of the second memory cell array via gaps, respectively.

3. The memory according to claim 1 , wherein
the first interconnection, the first memory cell array, the second interconnection and the second memory cell array are arranged in order along a first direction, and
the third interconnection extends in the first direction.

4. The memory according to claim 3 , further comprising:
a plurality of first word lines and second word lines stacked above the semiconductor substrate, wherein
first contacts for the first word lines are located on a first side of the first memory cell array, and
second contacts for the second word lines are located on a second side of the first memory cell array opposite to the first side in a second direction, the second direction crossing the first direction.

5. The memory according to claim 4 , further comprising:
a control circuit configured to control voltages applied to the first word lines through the first contacts and to the second word lines through the second contacts.

6. The memory according to claim 4 , wherein
the first word lines have a stair shape on a side facing away from the second word lines, and the first contacts are formed on upper surfaces of the first word lines that are exposed by the stair shape, and
the second word lines have a stair shape on a side facing away from the first word lines, and the second contacts are formed on upper surfaces of the second word lines that are exposed by the stair shape.

7. The memory according to claim 4 , wherein
parts of the first and second word lines at a first level above the semiconductor substrate are controlled separately, and
other parts of the first and second word lines at a second level above the semiconductor substrate are controlled separately.

8. The memory according to claim 7 , wherein
each of the first and second word lines has a planar shape, and
the part of the first word line has a first protruding portion that protrudes towards the second word line, and
the part of the second word line has a second protruding portion that protrudes towards the first word line.

9. The memory according to claim 8 , wherein
the first protruding portion and the second protruding portion are adjacent to each other along the first direction.

10. The memory according to claim 7 , wherein
the first memory cell array includes a plurality of memory strings, each of the memory strings including memory cells that are electrically connected in series and have gates that are electrically connected to the first word lines and the second word lines.

11. The memory according to claim 10 , wherein
the memory strings have a U-shape.

12. The memory according to claim 3 , wherein
the first interconnect and the second interconnect extend in a second direction, the second direction crossing the first direction.

13. The memory according to claim 12 , further comprising:
a fourth interconnect extending in the first direction, and connecting one end of the first interconnect and one end of the second interconnect.

14. The memory according to claim 13 , further comprising:
a fifth interconnect extending in the first direction, and connecting the other end of the first interconnect and the other end of the second interconnect.

15. The memory according to claim 1 , further comprising:
a plurality of word lines electrically connected to memory cells of the first memory cell array, wherein
the first interconnect includes a plurality of first interconnects disposed at levels corresponding to those of the word lines, and
the second interconnect includes a plurality of second interconnects disposed at levels corresponding to those of the word lines.

16. The memory according to claim 15 , further comprising:
a control circuit configured to apply a voltage sequentially to the first interconnects and the second interconnects.

Assignees

• Toshiba Memory Corp

Inventors

• Hishida Tomoo
• Murakami Sadatoshi
• Katsumata Ryota
• Iwase Masao

Classifications

• H01L21/823437

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10D84/0135

  Manufacturing their gate conductors · CPC title