Fin field-effect transistor device and method

Patent metadata

Field	Value
Publication number	US-12376357-B2
Application number	US-202217678554-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Jul 9, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

First claim

What is claimed is:

1. A method comprising:
depositing an interlayer dielectric (ILD) over a source/drain region;
implanting impurities into a portion of the ILD;
recessing the portion of the ILD to form a trench;
forming spacers on sidewalls of the trench, the spacers comprising a spacer material;
forming a source/drain contact in the trench; and
removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, wherein the etching process selectively etches the spacer material and the impurity, and wherein the air-gap is disposed between the source/drain contact and the source/drain region.

2. The method of claim 1 , wherein the impurities are silicon impurities.

3. The method of claim 1 , wherein the spacer material is silicon.

4. The method of claim 3 , wherein the etching process comprises etching the spacers and the portion of the ILD with a mixture of nitric acid (HNO 3 ) and hydrofluoric acid (HF) as etchants.

5. The method of claim 1 further comprising depositing a dielectric layer over the air-gap and the source/drain contact to seal the air-gap.

6. The method of claim 1 , wherein the source/drain region is disposed in a first fin, the first fin being adjacent to a second fin, the method further comprising:
forming a gate structure over the first fin and the second fin, wherein the source/drain contact overlaps the first fin and the second fin.

7. The method of claim 1 , wherein the spacers on the sidewalls of the trench are disposed above a topmost surface of the source/drain region.

8. A method comprising:
forming a first dielectric layer over an interlayer dielectric (ILD), a source/drain region, and a gate structure, the interlayer dielectric (ILD) surrounding the gate structure;
etching the first dielectric layer to form a first portion of a trench and expose the ILD;
performing an implantation process on the exposed ILD;
etching a first portion of the ILD to form a second portion of the trench;
forming a semiconductor layer on sidewalls of the second portion of the trench;
forming a second dielectric layer in the second portion of the trench;
forming a source/drain contact in the second portion of the trench, wherein sidewalls of the second dielectric layer are disposed between the semiconductor layer and the source/drain contact, wherein a second portion of the ILD is disposed between the second dielectric layer and the source/drain region, and between the source/drain contact and the source/drain region; and
removing the semiconductor layer and the second portion of the ILD to form an air-gap, a first portion of the air-gap extending along sidewalls of the source/drain contact, a second portion of the air-gap disposed under the source/drain contact.

9. The method of claim 8 further comprising:
recessing the gate structure below a top surface of the ILD; and
forming a gate mask over the recessed gate structure, wherein a top surface of the gate mask is level with a top surface of the ILD.

10. The method of claim 9 , wherein the materials of the ILD and the gate mask are different.

11. The method of claim 10 further comprising:
forming a metal layer in the second portion of the trench, wherein sidewalls of the metal layer are disposed between the second dielectric layer and the source/drain contact.

12. The method of claim 8 , wherein the semiconductor layer comprises silicon.

13. The method of claim 12 , wherein performing the implantation process on the exposed ILD introduces silicon impurities into the ILD.

14. The method of claim 13 , wherein removing the semiconductor layer and the second portion of the ILD further comprises performing an etching process that is selective to silicon and silicon doped materials.

15. The method of claim 14 , wherein the etching process comprises a wet etch process performed with a mixture of nitric acid (HNO 3 ) and hydrofluoric acid (HF) as etchants.

16. A method comprising:
forming an interlayer dielectric (ILD) over a source/drain region;
modifying a top portion of the ILD by introducing impurities into the top portion of the ILD;
selectively etching the top portion of the ILD to form a trench that is disposed over a bottom portion of the ILD;
forming first spacers on sidewalls of the trench;
forming second spacers on sidewalls of the first spacers in the trench;
forming a source/drain contact in the trench, wherein the bottom portion of the ILD is disposed between the source/drain contact and the source/drain region, and between the first spacers and the source/drain region; and
etching the first spacers to form a first portion of an air-gap extending along sidewalls of the source/drain contact.

17. The method of claim 16 further comprising etching the bottom portion of the ILD to form a second portion of the air-gap that is disposed under the source/drain contact.

18. The method of claim 16 , wherein the impurities are silicon impurities.

19. The method of claim 18 , wherein after modifying the top portion of the ILD, an impurity concentration of the ILD is in a range from 5×10 20 atoms/cm 3 to 3×10 21 atoms/cm 3 .

20. The method of claim 16 , wherein the first spacers comprise silicon.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeong Sai-Hooi
• LEE Kai-Hsuan
• Chui Chi On

Classifications

• H10P50/283 Primary

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title