Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12356726-B2
Application number	US-202318192712-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Oct 2, 2019
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming active regions on a substrate including a standard cell region that includes standard cells and a filler cell region that includes a filler cell, wherein the filler cell is between a first standard cell and a second standard cell of the standard cells;
forming gate lines intersecting the active regions and extending in a first direction that is parallel to an upper surface of the substrate;
forming filler contacts, wherein the filler contacts comprises at least one wiring filler contact that is connected to at least one of the active regions in the filler cell region and extends in the first direction;
forming a via structure in contact with the at least one wiring filler contact in the filler cell region; and
forming a lower wiring pattern in contact with an upper surface of the via structure in the filler cell region and extending into the standard cell region in a second direction intersecting the first direction,
wherein the at least one wiring filler contact is above the substrate and is below the lower wiring pattern.

2. The method of claim 1 , further comprising:
forming power wiring patterns along boundaries of the standard cell region extending in the second direction,
wherein the power wiring patterns are on a level equal to a level of the lower wiring pattern.

3. The method of claim 1 , further comprising:
forming active contacts connected to at least one of the active regions in the standard cell region and extending in the first direction,
wherein the active contacts and the filler contacts are formed by a same process.

4. The method of claim 3 , wherein a length of the at least one wiring filler contact is longer than a length of each of the active contacts in the first direction, and wherein the at least one wiring filler contact in the filler cell region is electrically connected to at least one of the active contacts in the standard cell region by the lower wiring pattern.

5. The method of claim 1 , wherein the filler contacts and the lower wiring pattern are formed of different materials.

6. The method of claim 1 , wherein the upper surface of the via structure is below the lower wiring pattern, and wherein a lower surface of the via structure is above the at least one wiring filler contact.

7. The method of claim 1 , further comprising:
forming a power wiring pattern extending in the second direction along boundaries of the first and second standard cells,
wherein the power wiring pattern is on a level equal to a level of the lower wiring pattern of each of the first and second standard cells.

8. A method of manufacturing a semiconductor device, the method comprising:
providing first and second standard cells on a substrate, each of the first and second standard cells comprising an active region and a lower wiring pattern electrically connected to the active region, with the active region between the lower wiring pattern and the substrate; and
providing a filler cell that is between the first and second standard cells, the filler cell comprising a filler active region and a filler contact that is electrically connected to the filler active region and extends longitudinally in a first direction,
wherein the first and second standard cells are spaced apart from each other in a second direction that intersects the first direction, wherein the lower wiring pattern of each of the first and second standard cells extends into the filler cell and is electrically connected to the filler contact, and wherein the filler contact is below the lower wiring pattern of each of the first and second standard cells and is above the filler active region.

9. The method of claim 8 , further comprising:
forming an active contact connected to the active region of at least one of the first and second standard cells and extending in the first direction,
wherein a length of the filler contact is longer than a length of the active contact in the first direction.

10. The method of claim 9 , wherein the active contact and the filler contact are formed by a same process.

11. The method of claim 8 , wherein the filler contact and the lower wiring pattern of each of the first and second standard cells are formed of different materials.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sungok
• Park Sangdo
• Seomun Jun
• Lee Bonghyun

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/975

  Wiring regions or routing · CPC title