Semiconductor Chip and Method for Manufacturing the Same
US-2017358600-A1 · Dec 14, 2017 · US
Wiring regions or routing
Wiring regions or routing · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D84/975 |
| Official title | {Wiring regions or routing} |
| Display label | Wiring regions or routing |
| Total patents | 815 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 21 |
| 2016 | 26 |
| 2017 | 71 |
| 2018 | 91 |
| 2019 | 110 |
| 2020 | 79 |
| 2021 | 91 |
| 2022 | 65 |
| 2023 | 79 |
| 2024 | 80 |
| 2025 | 78 |
| 2026 | 24 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Metal track cutting in standard cell layouts
US-9837398-B1 · Dec 5, 2017 · US
Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
US-9831141-B1 · Nov 28, 2017 · US
Method, apparatus, and system for improved cell design having unidirectional metal layout architecture
US-2017323902-A1 · Nov 9, 2017 · US
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells
US-9766970-B1 · Sep 19, 2017 · US
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
US-9761575-B1 · Sep 12, 2017 · US
Semiconductor device and method of manufacturing the same
US-9748238-B2 · Aug 29, 2017 · US
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
US-9728553-B1 · Aug 8, 2017 · US
Row driver fault isolation circuitry for matrix type integrated circuit
US-2017223283-A1 · Aug 3, 2017 · US
Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture
US-9704760-B2 · Jul 11, 2017 · US
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
US-2017170194-A1 · Jun 15, 2017 · US
Hybrid diffusion standard library cells, and related systems and methods
US-2017083653-A1 · Mar 23, 2017 · US
Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US-9536899-B2 · Jan 3, 2017 · US
Semiconductor Chip and Method for Manufacturing the Same
US-2016379991-A1 · Dec 29, 2016 · US
Integrated circuit (ic) with offset gate sidewall contacts and method of manufacture
US-2016379893-A1 · Dec 29, 2016 · US
Cross-couple in multi-height sequential cells for uni-directional m1
US-2016351490-A1 · Dec 1, 2016 · US
Integrated circuit, semiconductor device based on intergrated circuit, and standard cell library
US-2016351583-A1 · Dec 1, 2016 · US
Semiconductor device and method of manufacturing the same
US-2016322355-A1 · Nov 3, 2016 · US
Semiconductor device
US-2016322383-A1 · Nov 3, 2016 · US
Conductive line patterning
US-9472501-B2 · Oct 18, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D84/975?
- CPC H10D84/975 is the Cooperative Patent Classification code for “Wiring regions or routing.”
- How many patents are filed under CPC H10D84/975 (Wiring regions or routing)?
- Our database includes 815 publications tagged with this CPC code.
- Is patent activity under CPC H10D84/975 growing?
- Publication counts under this code: 80 in 2024 vs 78 in 2025 (latest complete years).