Integrated circuit including standard cells overlapping each other and method of generating layout of the integrated circuit

Patent metadata

Field	Value
Publication number	US-2018365368-A1
Application number	US-201815933958-A
Country	US
Kind code	A1
Filing date	Mar 23, 2018
Priority date	Jun 14, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

First claim

1 . An integrated circuit comprising:
a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction, wherein a BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

2 . The integrated circuit of claim 1 , wherein the plurality of standard cells further comprise a second standard cell adjacent to the first standard cell in the second horizontal direction, and
an FEOL region of the second standard cell including a first step section overlapping the eaves section of the first standard cell in the vertical direction and protruding in direction antiparallel to the second horizontal direction.

3 . The integrated circuit of claim 2 , further comprising:
a single diffusion break extending in the first horizontal direction between the FEOL region of the first standard cell and the FEOL region of the second standard cell.

4 . The integrated circuit of claim 2 , wherein a BEOL region of the second standard cell includes an eaves section not overlapping the FEOL region of the second standard cell in the vertical direction, the eaves section protruding in the second horizontal direction, and
a length of the eaves section of the second standard cell in the second horizontal direction is the same as a length of the first step section of the second standard cell in the second horizontal direction.

5 . The integrated circuit of claim 2 , wherein the FEOL region of the second standard cell further includes a second step section not overlapping a BEOL region of the second standard cell in the vertical direction, the second step section protruding in the second horizontal direction, and
a length of the second step section of the second standard cell in the second horizontal direction is the same as a length of the first step section of the second standard cell in the second horizontal direction.

6 . The integrated circuit of claim 1 , wherein the plurality of standard cells further comprise a third standard cell adjacent to the first standard cell in the second horizontal direction, and
a BEOL region of the third standard cell comprises an eaves section not overlapping an FEOL region of the third standard cell in the vertical direction, the eaves section protruding in a direction antiparallel to the second horizontal direction.

7 . The integrated circuit of claim 6 , further comprising:
a double diffusion break extending in the first horizontal direction between the FEOL region of the first standard cell and the FEOL region of the third standard cell, the double diffusion break overlapping the eaves sections of the first and third standard cells in the vertical direction.

8 . The integrated circuit of claim 1 , wherein the FEOL region of the first standard cell includes a step section not overlapping the BEOL region of the first standard cell in the vertical direction, the step section protruding in a direction antiparallel to the second horizontal direction, and
a length of the step section of the first standard cell in the second horizontal direction is the same as a length of the first standard cell in the second horizontal direction.

9 . The integrated circuit of claim 8 , wherein the plurality of standard cells further include a fourth standard cell adjacent to the first standard cell in direction antiparallel to the second horizontal direction, and
an FEOL region of the fourth standard cell include a step section not overlapping a BEOL region of the fourth standard cell in the vertical direction, the step section protruding in the second horizontal direction.

10 . The integrated circuit of claim 9 , further comprising:
a single diffusion break extending in the first horizontal direction between the FEOL region of the first standard cell and the FEOL region of the fourth standard cell.

11 . The integrated circuit of claim 9 , further comprising:
at least one pattern extending in the second horizontal direction between the BEOL region of the first standard cell and the BEOL region of the fourth standard cell and connecting power lines of the first and fourth standard cells.

12 . The integrated circuit of claim 8 , wherein the plurality of standard cells further comprise a fifth standard cell adjacent to the first standard cell in direction antiparallel to the second horizontal direction,
a BEOL region of the fifth standard cell comprises a first eaves section and a second eaves section which do not overlap an FEOL region of the fifth standard cell in the vertical direction, the first and second eaves sections respectively protruding in the second horizontal direction and the direction antiparallel to the second horizontal direction and having the same length in the second horizontal direction, and the first eaves section of the fifth standard cell overlaps the step section of the first standard cell in the vertical direction.

13 . The integrated circuit of claim 8 , wherein the FEOL region of the first standard cell further comprises at least one transistor and at least one contact structure configured to transmit a power supply voltage to the at least one transistor, and
the at least one contact structure is adjacent to the step section of the first standard cell.

14 . The integrated circuit of claim 1 , wherein the plurality of standard cells further comprise a sixth standard cell symmetrical with the first standard cell with respect to an axis parallel with the first horizontal direction, the sixth standard cell providing the same function as the first standard cell, and
a BEOL region of the sixth standard cell comprises an eaves section protruding in a direction antiparallel to the second horizontal direction.

15 . The integrated circuit of claim 1 , wherein the plurality of standard cells further comprise a seventh standard cell of which an FEOL region and a BEOL region are stacked in the same size and manner as the FEOL and BEOL regions of the first standard cell, the seventh standard cell having a pin placement that is different from a pin placement of the first standard cell.

16 . The integrated circuit of claim 15 , wherein the FEOL region of the seventh standard cell is symmetrical with the FEOL region of the first standard cell with respect to an axis parallel with the first horizontal direction.

17 . (canceled)

18 . (canceled)

19 . An integrated circuit comprising:
a plurality of first standard cells each including a first front-end-of-line (FEOL) region and a first back-end-of-line (BEOL) region on the first FEOL region, the first FEOL region including at least one gate line extending in a first horizontal direction, the first standard cells being consecutively placed in a second horizontal direction perpendicular to the first horizontal direction, wherein the first BEOL region of each of the first standard cells overlaps, in a vertical direction, at least part of a first FEOL region of another first standard cell adjacent in the second horizontal direction.

20 . The integrated circuit of claim 19 , wherein the first FEOL region comprises a step section protruding in a direction antiparallel to the second horizontal direction and not overlapping the first BEOL region in the ver

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Jung Jong-Hoon
• Yu Ji-Su
• Lee Seung-Young
• Song Tae-Joong
• Lee Jae-Boong

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title