Computer implemented methods and computing systems for designing integrated circuits by considering back-end-of-line

Patent metadata

Field	Value
Publication number	US-2018231604-A1
Application number	US-201715842184-A
Country	US
Kind code	A1
Filing date	Dec 14, 2017
Priority date	Feb 10, 2017
Publication date	Aug 16, 2018
Grant date	—

Abstract

Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

First claim

What is claimed is:

1 . A computer, implemented method of designing an integrated circuit including logic modules, the method performed by a processor and comprising:
performing a placement and routing (P&R) operation for standard cells defining the integrated circuit; extracting characteristic values from a result of the P&R operation; generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups of the logic modules based on the extracted characteristic values; and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit based on the generated physical-aware annotation file.

2 . The computer implemented method of claim 1 , wherein the extracting of the characteristic values from the result of the P&R operation comprises extracting clock latency information with respect to ones of a plurality of clock pins from the result of the P&R operation as the characteristic values.

3 . The computer implemented method of claim 2 , wherein the clock latency information comprises a maximum clock latency and a minimum clock latency with respect to the ones of the plurality of clock pins.

4 . The computer implemented method of claim 2 , wherein the generating of the physical-aware annotation file comprises:
grouping the logic modules included in the integrated circuit into the plurality of groups; and determining clock latency average values, respectively corresponding to the plurality of groups, as the plurality of representative characteristic values, respectively corresponding to the plurality of groups.

5 . The computer implemented method of claim 4 , wherein the performing of the physical-aware synthesis operation comprises:
applying, to the plurality of clock pins included in the integrated circuit, a reference clock latency corresponding to an average value of all clock latencies; and further applying, to clock pins included in the logic modules of each of-the plurality of groups, a representative characteristic value corresponding to the ones of the plurality of groups.

6 . The computer implemented method of claim 2 , wherein the performing of the P&R operation for the standard cells defining the integrated circuit is based on the netlist and the clock latency information.

7 . The computer implemented method of claim 6 , wherein the performing of the P&R operation comprises:
placing the standard cells based on the netlist and the clock latency information; after placing the standard cells, removing the clock latency information; after removing the clock latency information, performing a clock tree synthesis operation with respect to a result of the placing; and performing a routing operation with respect to a result of the clock tree synthesis operation.

8 . The computer implemented -method of claim 1 , wherein in the extracting of the characteristic values, parasitic component information, including information about at least one of parasitic resistance and a parasitic capacitance, on each of a plurality of signal nets, is extracted from the result of the P&R operation as the characteristic values.

9 . The computer implemented method of claim 8 , wherein the extracting of the characteristic values comprises:
estimating first parasitic components from a result of a global routing of the P&R operation; extracting second parasitic components from a result of a detail routing of the P&R operation; and generating parasitic scaling factors by comparing the first parasitic components with the second parasitic components.

10 . The computer implemented method of claim 9 , wherein the generating of the physical-aware annotation file comprises;
grouping the plurality of signal nets into the plurality of groups; and determining representative parasitic scaling factors that respectively correspond to the plurality of groups, based on the generated parasitic scaling factors.

11 . The computer implemented method of claim 10 , wherein the grouping of the plurality of signal nets into the plurality of groups is based on at least one of a number of fanout pins, a length of a net, a direct connection status between a net and an Input/Output (I/O) cell, and a direct connection status between a net and a macro cell.

12 . A computer implemented method of designing an integrated circuit, the method performed by a processor and comprising:
performing a first placement and routing (P&R) operation for a plurality of standard cells defining the integrated circuit; extracting at least one of clock latency information and parasitic component Information from a result, of the first P&R operation; performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the extracted at least one of clock latency information and parasitic component information; and performing a second P&R operation for the plurality of standard cells defining the integrated circuit, according to the generated netlist.

13 . The computer implemented method of claim 12 , wherein the extracted at least one of clock latency information and parasitic component information comprises extracted clock latency information, the method further comprising:
generating a clock latency annotation file by determining a plurality of representative clock latencies that respectively correspond to a plurality of groups, based on the extracted clock latency information, wherein in the performing of the physical-aware synthesis operation, the physical-aware synthesis operation is performed using the clock latency annotation file.

14 . The computer implemented method of claim 12 , wherein the extracted at least one of clock latency information and parasitic component information comprises extracted parasitic component information, the method further comprising:
generating a parasitic component annotation file by determining a plurality of representative parasitic scaling factors that respectively correspond to a plurality of groups of logic modules included in the integrated circuit, based on the extracted parasitic component information, wherein in the performing of the physical-aware synthesis operation, the physical-aware synthesis operation is performed using the parasitic component annotation file.

15 . The computer implemented method of claim 12 ,
wherein the performing of the first P&R operation is based on a first netlist for the integrated circuit, wherein the extracting comprises extracting the clock latency information from the result of the first P&R operation, wherein the netlist generated by the performing of the physical-aware synthesis operation is a second netlist, and wherein the performing of the second P&R operation comprises placing the plurality of standard cells defining the integrated circuit, based on the extracted clock latency information.

16 . A computer implemented method of designing an integrated circuit, the method performed by a processor and comprising:
performing a first placement and routing (P&R) operation to place a first plurality of standard cells defining the integrated circuit; extracting clock latency information from a result of the first P&R operation; and performing a second P&R operation to place a second plurality of standard cells defining the integrated circuit based on the clock latency information.

17 . The computer implemented method of claim 16 ,
wherein the first P&R operation is based on a first netlist for the integ

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tae-Il
• Kim Jae-Hoon
• Kim Hyung-Ock
• Choi Jung-Yun

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title