Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-2019164993-A1
Application number	US-201916262183-A
Country	US
Kind code	A1
Filing date	Jan 30, 2019
Priority date	Aug 1, 2016
Publication date	May 30, 2019
Grant date	—

Abstract

Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

First claim

What is claimed is:

1 . A semiconductor integrated circuit device, comprising:
a first standard cell including a nanowire field effect transistor (FET) and having a logical function; and a second standard cell disposed adjacent to the first standard cell in a first direction and having no logical function,
wherein
the nanowire FET includes:
a nanowire extending in the first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires; and
a pair of pads that are respectively arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire, and
the second standard cell includes a dummy pad having no contribution to a logical function of a circuit.

2 . The semiconductor integrated circuit device of claim 1 , wherein
the dummy pad and the pair of pads have an equal pad width as a dimension in the first direction, have an equal pad height as a dimension in a second direction perpendicular to the first direction, and/or have a same position in the second direction.

3 . The semiconductor integrated circuit device of claim 1 , wherein
the dummy pad and the pair of pads are arranged at an equal pitch in the first direction.

4 . The semiconductor integrated circuit device of claim 1 , wherein
the dummy pad includes first and second dummy pads arranged in the first direction, and the second standard cell includes a second nanowire provided between the first and second dummy pads and extending in the first direction, the second nanowire being a single nanowire or a plurality of parallelly arranged nanowires.

5 . The semiconductor integrated circuit device of claim 1 , wherein
the second standard cell includes:
a dummy gate line disposed at a cell end in the first direction; and
a second nanowire provided between the dummy pad and the dummy gate line and extending in the first direction, the second nanowire being a single nanowire or a plurality of being parallelly arranged nanowires.

6 . The semiconductor integrated circuit device of claim 1 , wherein
the first and second standard cells are supplied with first and second power supply potentials, and the dummy pad includes a first dummy pad supplied with the first power supply potential.

7 . The semiconductor integrated circuit device of claim 6 , wherein
the first dummy pad includes two dummy pads arranged in the first direction, the second standard cell includes a dummy gate line extending in a second direction perpendicular to the first direction between the two dummy pads, and the dummy gate line is supplied with the second power supply potential.

8 . The semiconductor integrated circuit device of claim 6 , wherein
the first dummy pad includes two dummy pads arranged in the first direction, the second standard cell includes:
a second nanowire provided between the two dummy pads and extending in the first direction, the second nanowire being a single nanowire or including a plurality of parallelly arranged nanowires; and
a gate line extending in a second direction perpendicular to the first direction and surrounding a periphery of the second nanowire within a predetermined range of the second nanowire in the first direction, and
the gate line is supplied with the second power supply potential.

9 . The semiconductor integrated circuit device of claim 6 , wherein
the dummy pad includes a second dummy pad supplied with the second power supply potential.

10 . The semiconductor integrated circuit device of claim 9 , wherein
the first dummy pad includes two dummy pads arranged in the first direction, the second dummy pad includes two dummy pads arranged in the first direction, the second standard cell includes:
a first dummy gate line extending in a second direction perpendicular to the first direction between the two dummy pads included in the first dummy pad; and
a second dummy gate line extending in the second direction between the two dummy pads included in the second dummy pad,
the first dummy gate line is supplied with the second power supply potential, and the second dummy gate line is supplied with the first power supply potential.

11 . The semiconductor integrated circuit device of claim 10 , wherein
the first dummy gate line and the second dummy gate line are aligned in the second direction.

12 . The semiconductor integrated circuit device of claim 1 , wherein
the second standard cell is a filler cell or a cell-row-terminating cell.

Assignees

• Socionext Inc

Inventors

• Shimbo Hiroyuki

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L2027/11866

  Electricity · mapped topic

• H01L2027/11812

  Electricity · mapped topic

• H01L2027/11864

  Electricity · mapped topic

• H01L2027/11861

  Electricity · mapped topic