Integrated circuit and layout method for standard cell structures

Patent metadata

Field	Value
Publication number	US-2019155984-A1
Application number	US-201815965358-A
Country	US
Kind code	A1
Filing date	Apr 27, 2018
Priority date	Nov 21, 2017
Publication date	May 23, 2019
Grant date	—

Abstract

Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

First claim

What is claimed is:

1 . A method of placing and routing standard cell structures, the method comprising:
determining first and second directions of a plurality of standard cell structures, wherein the first and second directions are perpendicular to each other; determining locations of a plurality of power supply lines, wherein the plurality of power supply lines extend along the second direction and provide electrical supply to the plurality of standard cell structures: determining a first height of a first standard cell structure and a second height of a second standard cell structure of the plurality of standard cell structures, wherein the first and second heights are measured in the second direction and are different from each other; and arranging at least one of the first and second standard cell structures in the second direction, wherein at least one of the determining the first and second directions, the determining locations, the determining the first height, and the arranging is performed by a processor.

2 . The method of claim 1 , wherein the arranging abuts the first and second standard cell structures with each other in the second direction.

3 . The method of claim 1 , wherein the arranging reduces a gap between the first and second standard cell structures.

4 . The method of claim 3 , wherein a height of the gap is about half of the first height.

5 . The method of claim 1 , wherein the arranging the at least one of the first and second standard cell structures is based on the first and second heights.

6 . The method of claim 1 , wherein the plurality of standard cell structures comprises one or more fin field-effect transistors (finFETs), and the second direction is parallel with the gate structures of the one or more finFETs.

7 . The method of claim 1 , wherein the arranging comprises moving the first and second standard cell structures along the second direction.

8 . The method of claim 1 , wherein the arranging comprises rotating at least one of the first and second standard cell structures.

9 . The method of claim 8 , wherein rotating at least one of the first and second standard cell structures comprises rotating around a respective axis of symmetry of the first and second standard cells.

10 . A standard cell structure, comprising:
a first fin field-effect transistor (finFET) having a first fin, wherein the first fin comprises a first source/drain contact formed thereon; a second finFET having a second fin, wherein the second fin comprises a second source/drain contact formed thereon, wherein the first and second fins are parallel with each other; and a first power supply line perpendicular to the first or second fin.

11 . The standard cell structure of claim 10 , wherein the first power supply line is electrically, connected to the first source/drain contact.

12 . The standard cell structure of claim 10 , further comprising a second power supply line, wherein the second power supply line is perpendicular to the first or second fin.

13 . The standard cell structure of claim 12 , wherein the second power supply line is electrically connected to the second source/drain contact.

14 . The standard cell structure of claim 12 , wherein the first power supply line comprises a supply voltage and the second power supply line comprises a reference voltage.

15 . The standard cell structure of claim 10 , further comprising a gate structure on the first and second fins.

16 . A method of placing and routing standard cell structures, the method comprising:
determining a first location for a first pin connector of a first standard cell structure, wherein the first standard cell structure comprises a first portion of an active region extending along a direction and the first pin connector is electrically connected to the active region; determining a second location for a second pin connector of a second standard cell structure, wherein the second standard cell structure comprises a second portion of active region extending along the direction and the second pin connector is electrically connected to the active region; determining a third location for a third pin connector of a third standard cell structure such that a power supply line electrically connecting the second and third pin connectors is perpendicular to the direction; and performing an action on at least one of the first and second standard cell structures along the direction such that a distance between the first and second locations is reduced, wherein at least one of the determining the first location, the determining the second location, the determining the third location, and the performing is performed by a processor.

17 . The method of claim 16 , wherein performing the action comprises moving at least one of the first and second standard cell structures along the direction, wherein the direction is perpendicular to a gate structure of the first standard cell structure.

18 . The method of claim 16 , wherein performing the action comprises moving at least one of the first and second standard cell structures along the direction ; wherein the direction is parallel to a fin structure of the first standard cell structure.

19 . The method of claim 16 , wherein performing the action comprises rotating the first or second standard cell structure.

20 . The method of claim 19 , wherein rotating the first or second standard cell structure comprises rotating around an axis of symmetry of the first or second standard cells.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Sheng-Hsiung
• Lin Chung-Te
• Chang Fong-Yuan
• Yu Ho Che
• Tien Li-Chun

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0207

  Electricity · mapped topic

• G06F17/5077

  Physics · mapped topic