Power rail inbound middle of line (MOL) routing

Patent metadata

Field	Value
Publication number	US-9935100-B2
Application number	US-201514936459-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Nov 9, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

First claim

What is claimed is:

1. A semiconductor die, comprising:
a power rail;
a first gate;
a second gate;
a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer;
a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer; and
an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, the interconnect extends laterally between a sidewall of the first gate contact and a sidewall of the second gate contact, and at least a portion of the interconnect is underneath the power rail, wherein the power rail is formed from an M 1 metal layer, and the M 1 metal layer is above the first and second MOL metal layers.

2. The semiconductor die of claim 1 , wherein the interconnect makes contact with the sidewalls of the first and second gate contacts.

3. The semiconductor die of claim 1 , further comprising:
a source, wherein the interconnect is electrically coupled to the source; and
a via electrically coupled between the interconnect and the power rail.

4. The semiconductor die of claim 3 , further comprising a source contact disposed between the source and the interconnect.

5. The semiconductor die of claim 4 , wherein the source contact comprises trench silicide.

6. The semiconductor of claim 3 , wherein the source and the first gate are part of a p-type field effect transistor (PFET), and the power rail has a supply voltage of Vdd.

7. The semiconductor die of claim 6 , wherein the interconnect ties the source and the first gate together to the power rail to turn off the PFET.

8. The semiconductor of claim 3 , wherein the source and the first gate are part of an n-type field effect transistor (NFET), and the power rail is grounded.

9. The semiconductor die of claim 1 , further comprising:
a first source, wherein the first source and the first gate are part of a first transistor;
a second source, wherein the second source and the second gate are part of a second transistor, and the interconnect is electrically coupled to the first source and the second source; and
a via electrically coupled between the interconnect and the power rail.

10. The semiconductor die of claim 1 , further comprising:
a source/drain;
a source/drain contact electrically coupled to the source/drain, wherein the source/drain contact is formed from the second MOL metal layer; and
a via electrically coupled between the source/drain contact and the power rail.

11. The semiconductor die of claim 8 , wherein the interconnect ties the source and the first gate together to the power rail to turn off the NFET.

12. The semiconductor die of claim 1 , wherein the interconnect passes over a third gate, and the third gate is between the first and second gates.

13. A semiconductor die, comprising:
a power rail;
a first gate;
a second gate;
a third gate, wherein the third gate is between the first and second gates;
a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer;
a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer; and
an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, the interconnect passes over the third gate, and at least a portion of the interconnect is underneath the power rail, wherein the power rail is formed from an M 1 metal layer, and the M 1 metal layer is above the first and second MOL metal layers.

14. The semiconductor die of claim 13 , wherein the interconnect makes contact with sidewalls of the first and second gate contacts.

15. The semiconductor die of claim 13 , wherein the first gate is in a first cell, and the second gate is in a second cell.

Assignees

• Qualcomm Inc

Inventors

• Lim Hyeokjin Bruce
• Duan Zhengyu
• Ye Qi
• Malabry Mickael

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title