Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer

Patent metadata

Field	Value
Publication number	US-12322594-B2
Application number	US-202418748489-A
Country	US
Kind code	B2
Filing date	Jun 20, 2024
Priority date	Apr 21, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

First claim

The invention claimed is:

1. A method for making a semiconductor device comprising:
forming a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent;
forming a second single crystal silicon layer having a second percentage of silicon 28 greater than 95 percent;
forming at least one quantum bit device associated with the second single crystal silicon layer; and
forming a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

2. The method of claim 1 , wherein forming the at least one quantum bit device comprises forming an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer.

3. The method of claim 1 , wherein the non-semiconductor monolayer comprises oxygen.

4. The method of claim 1 , wherein forming the superlattice comprises forming the superlattice between the first and second single crystal silicon layers.

5. The method of claim 1 , wherein the second percentage of silicon 28 is greater than 99 percent.

6. The method of claim 1 , further comprising forming a third single crystal silicon layer between the first single crystal silicon layer and the superlattice and having a third percentage of silicon 28 higher than 93 percent.

7. The method of claim 1 , further comprising forming a third single crystal silicon layer between the superlattice and the second single crystal silicon layer.

8. The method of claim 1 , wherein forming the superlattice comprises forming a first superlattice layer above the first single crystal silicon layer; and further comprising:
forming a third single crystal silicon layer above the first superlattice layer; and
forming a second superlattice layer above the third single crystal silicon layer and below the second single crystal silicon layer.

9. The method of claim 8 , wherein forming the first superlattice layer comprises forming the first superlattice layer on the first single crystal silicon layer; and wherein forming the second single crystal silicon layer comprises forming the second single crystal silicon layer on the second superlattice layer.

10. A method for making a semiconductor device comprising:
forming a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent;
forming a second single crystal silicon layer having a second percentage of silicon 28 greater than 99 percent;
forming at least one quantum bit device associated with the second single crystal silicon layer; and
forming a superlattice below the at least one quantum bit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

11. The method of claim 10 , wherein forming the at least one quantum bit device comprises forming an insulating layer on the second single crystal silicon layer, and a gate electrode on the insulating layer defining a hole or electron isolation area beneath the gate electrode in the second single crystal silicon layer.

12. The method of claim 10 , wherein forming the superlattice comprises forming the superlattice between the first and second single crystal silicon layers.

13. A method for making a semiconductor device comprising:
forming a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent;
forming a second single crystal silicon layer having a second percentage of silicon 28 greater than 95 percent;
forming at least one circuit device comprising
spaced apart source and drain regions in the second single crystal silicon layer defining a channel therebetween, and
a gate comprising a gate dielectric layer overlying the channel and a gate electrode overlying the gate dielectric layer; and

forming a superlattice below the at least one circuit device, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

14. The method of claim 13 , wherein the non-semiconductor monolayer comprises oxygen.

15. The method of claim 13 , wherein forming the superlattice comprises forming the superlattice between the first and second single crystal silicon layers.

16. The method of claim 13 , wherein the second percentage of silicon 28 is greater than 99 percent.

17. The method of claim 13 , further comprising forming a third single crystal silicon layer between the first single crystal silicon layer and the superlattice and having a third percentage of silicon 28 higher than 93 percent.

18. The method of claim 13 , further comprising forming a third single crystal silicon layer between the superlattice and the second single crystal silicon layer.

19. The method of claim 13 , wherein forming the superlattice comprises forming a first superlattice layer above the first single crystal silicon layer; and further comprising:
forming a third single crystal silicon layer above the first superlattice layer; and
forming a second superlattice layer above the third single crystal silicon layer and below the second single crystal silicon layer.

20. The method of claim 19 , wherein forming the first superlattice layer comprises forming the first superlattice layer on the first single crystal silicon layer;
and wherein forming the second crystal silicon layer comprises forming the second single crystal silicon layer on the second superlattice layer.

Assignees

• Atomera Inc

Inventors

• Hytha Marek
• Weeks Keith Doran
• Cody Nyles Wynn
• Takeuchi Hideki

Classifications

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3246

  Monolayers · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title