DRAM sense amplifier architecture with reduced power consumption and related methods

Patent metadata

Field	Value
Publication number	US-12267996-B2
Application number	US-202318311465-A
Country	US
Kind code	B2
Filing date	May 3, 2023
Priority date	May 4, 2022
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, with the third reference voltage being greater than the high logic voltage of the DRAM cell.

First claim

The invention claimed is:

1. A dynamic random access memory (DRAM) device comprising:
a DRAM cell comprising a capacitor and a bit cell pass gate transistor coupling the capacitor to a bit line;
a single-ended sense amplifier comprising:
a cross-coupled transistor sensing circuit comprising a first p-channel transistor coupled between a first terminal and a first line, a first n-channel transistor coupled between the first line and a second terminal, the first p-channel transistor and the first n-channel transistor each having a gate coupled to a second line, a second p-channel transistor coupled between the first terminal and the second line, and a second n-channel transistor coupled between the second terminal and the second line, the second p-channel transistor and the second n-channel transistor each having a gate coupled to the first line;
a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to the first line and the second line, respectively;
a refresh circuit configured to selectively apply a third reference voltage to the bit line, wherein the refresh circuit is controlled by a voltage on the second line; and
a bit line transistor directly coupling the bit line to the first line of the cross-coupled transistor sensing circuit, wherein the bit line is the only bit line coupled to the cross-coupled transistor sensing circuit.

2. The DRAM device of claim 1 wherein at least one of the first p-channel transistor, the first n-channel transistor, the second p-channel transistor and the second n-channel transistor comprises:
spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

3. The DRAM device of claim 1 wherein the refresh circuit comprises a transistor comprising spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

4. The DRAM device of claim 1 wherein the precharge circuit comprises at least one transistor comprising spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

5. The DRAM device of claim 1 , further comprising a programming circuit configured to provide write data to the first line and the second line during a write operation.

6. The DRAM device of claim 5 wherein the programming circuit comprises at least one transistor comprising spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

7. The DRAM device of claim 1 , wherein each of the first p-channel transistor, the first n-channel transistor, the second p-channel transistor and the second n-channel transistor comprises:
spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

8. A dynamic random access memory (DRAM) device comprising:
a plurality of stacked DRAM integrated circuits (IC) each DRAM IC comprising
an array of DRAM cells, each DRAM cell configured to store a high logic voltage and a low logic voltage,
a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively,
a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line, the sense amplifier comprising at least one transistor comprising
spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, the third reference voltage being greater than the high logic voltage of the DRAM cell.

9. The DRAM device of claim 8 further comprising a control IC coupled to the plurality of stacked DRAM ICs.

10. The DRAM device of claim 8 further comprising a power management IC coupled to the plurality of stacked DRAM ICs.

11. The DRAM device of claim 8 wherein the at least one transistor of the cross-coupled transistor sensing circuit comprises all transistors of the cross-coupled transistor sensing circuit.

12. The DRAM device of claim 8 wherein the refresh circuit comprises at least one transistor comprising spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

13. The DRAM device of claim 8 wherein the precharge circuit comprises at least one transistor comprising spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate overlying the superlattice channel, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

14. The DRAM device of claim 8 further

Assignees

• Atomera Inc

Inventors

• Roy Richard Stephen
• Mears Robert J

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• G11C7/067

  Single-ended amplifiers · CPC title