Apparatus and memory device including spiral tsv connection
US-2024413124-A1 · Dec 12, 2024 · US
Assemblies of multiple devices comprising at least one memory device covered by this subclass
Assemblies of multiple devices comprising at least one memory device covered by this subclass · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B80/00 |
| Official title | Assemblies of multiple devices comprising at least one memory device covered by this subclass |
| Display label | Assemblies of multiple devices comprising at least one memory device covered by this subclass |
| Total patents | 3,248 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly growing.
| Year | Patents |
|---|---|
| 2015 | 4 |
| 2016 | 2 |
| 2017 | 5 |
| 2018 | 15 |
| 2019 | 19 |
| 2020 | 37 |
| 2021 | 42 |
| 2022 | 64 |
| 2023 | 305 |
| 2024 | 907 |
| 2025 | 1,369 |
| 2026 | 479 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
3D Hybrid Bonding 3D Memory Devices with NPU/CPU for AI Inference Application
US-2024370715-A1 · Nov 7, 2024 · US
Semiconductor memory device
US-2024315058-A1 · Sep 19, 2024 · US
Semiconductor devices and data storage systems including the same
US-2024297117-A1 · Sep 5, 2024 · US
Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Memory stack structure including power distribution structures and a high-bandwidth memory including the memory stack structure
US-2024213219-A1 · Jun 27, 2024 · US
Semiconductor devices and electronic systems including the same
US-2024147722-A1 · May 2, 2024 · US
Semiconductor storage device
US-2024107765-A1 · Mar 28, 2024 · US
Semiconductor package with reinforcing structure
US-2024063077-A1 · Feb 22, 2024 · US
Non-volatile memory device
US-2024055469-A1 · Feb 15, 2024 · US
Semiconductor package
US-2024047418-A1 · Feb 8, 2024 · US
Semiconductor package
US-2024021575-A1 · Jan 18, 2024 · US
Semiconductor package with clock sharing and electronic system including the same
US-2020286531-A1 · Sep 10, 2020 · US
Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories
US-2020143866-A1 · May 7, 2020 · US
Memory system having combined high density, low bandwidth and low density, high bandwidth memories
US-10573368-B2 · Feb 25, 2020 · US
Direct-bonded native interconnects and active base die
US-10522352-B2 · Dec 31, 2019 · US
Self-aligned gate endcap (sage) architectures with gate-all-around devices
US-2019393352-A1 · Dec 26, 2019 · US
Interface bridge between integrated circuit die
US-2019361831-A1 · Nov 28, 2019 · US
Semiconductor device having interconnection in package and method for manufacturing the same
US-2019355407-A1 · Nov 21, 2019 · US
Semiconductor package
US-2019355667-A1 · Nov 21, 2019 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B80/00?
- CPC H10B80/00 is the Cooperative Patent Classification code for “Assemblies of multiple devices comprising at least one memory device covered by this subclass.”
- How many patents are filed under CPC H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass)?
- Our database includes 3,248 publications tagged with this CPC code.
- Is patent activity under CPC H10B80/00 growing?
- Publication counts under this code: 907 in 2024 vs 1,369 in 2025 (latest complete years).