Semiconductor package

Patent metadata

Field	Value
Publication number	US-12176262-B2
Application number	US-202318475926-A
Country	US
Kind code	B2
Filing date	Sep 27, 2023
Priority date	Oct 7, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, comprising:
forming a lower redistribution structure on a first carrier, the lower redistribution structure including a plurality of lower redistribution patterns having lower connection pads;
forming a protective insulating layer covering the lower connection pads;
attaching the lower redistribution structure on a second carrier so that a boundary surface, on which the plurality of lower redistribution patterns is exposed after removing the first carrier, faces upward;
forming an upper redistribution structure on the boundary surface of the lower redistribution structure, the upper redistribution structure including a plurality of upper redistribution patterns having upper connection pads electrically connected to the lower connection pads, wherein a first width of each of the lower connection pads is greater than a second width of each of the upper connection pads;
forming openings exposing at least a portion of each of the lower connection pads from the protective insulating layer;
disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate including a plurality of wiring patterns having lower wiring pads, the lower connection pads of the interposer substrate electrically connected to the plurality of wiring patterns of the base substrate through lower connection bumps disposed on the openings, wherein a third width of each of the lower wiring pads is greater than the first width of each of the lower connection pads; and
disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads of the interposer substrate through upper connection bumps.

2. The method of manufacturing the semiconductor package according to claim 1 , wherein the second width of each of the upper connection pads is in a range of in a range of 40 μm to 50 μm.

3. The method of manufacturing the semiconductor package according to claim 1 , wherein a distance between a pair of lower connection bumps among the lower connection bumps, adjacent to each other, is in a range of 0.1 mm to 0.7 mm.

4. The method of manufacturing the semiconductor package according to claim 1 , wherein a distance between a pair of upper connection bumps among the upper connection bumps, adjacent to each other, is in a range of 50 μm to 150 μm.

5. The method of manufacturing the semiconductor package according to claim 1 , further comprising, forming external connection bumps on the lower wiring pads of the base substrate,
wherein a distance between a pair of external connection bumps among the external connection bumps, adjacent to each other, is in a range of 0.8 mm to 1.5 mm.

6. The method of manufacturing the semiconductor package according to claim 1 ,
wherein a line width of the plurality of wiring patterns is in a range of 40 μm to 70 μm,
wherein a line width of the plurality of lower redistribution patterns is in a range of 7 μm to 20 μm, and
wherein a line width of the plurality of upper redistribution patterns is in a range of 5 μm to 10 μm.

7. The method of manufacturing the semiconductor package according to claim 1 ,
wherein a distance between a pair of lower redistribution patterns, from among the plurality of lower redistribution patterns, adjacent to each other, is in a range of 10 μm to 20 μm, and
wherein a distance between a pair of upper redistribution patterns, from among the plurality of upper redistribution patterns, adjacent to each other, is in a range of 5 μm to 10 μm.

8. The method of manufacturing the semiconductor package according to claim 1 ,
wherein the lower redistribution structure including a plurality of lower insulating layers, the plurality of lower redistribution patterns disposed on both sides of each of the plurality of lower insulating layers, and a plurality of lower redistribution vias electrically connecting the plurality of lower redistribution patterns to each other, and
wherein the upper redistribution structure including a plurality of upper insulating layers, the plurality of upper redistribution patterns disposed on one side of each of the plurality of upper insulating layers, and a plurality of upper redistribution vias electrically connecting the plurality of upper redistribution patterns to each other, and a lower redistribution pattern and an upper redistribution pattern adjacent to each other, among the plurality of lower redistribution patterns and the plurality of upper redistribution patterns.

9. The method of manufacturing the semiconductor package according to claim 8 , wherein the plurality of lower redistribution vias and the plurality of upper redistribution vias have shapes tapered in opposite directions to each other, based on the boundary surface.

10. The method of manufacturing the semiconductor package according to claim 8 , wherein the plurality of upper insulating layers includes a photosensitive resin, and
wherein the plurality of lower insulating layers includes a non-photosensitive resin.

11. The method of manufacturing the semiconductor package according to claim 8 , wherein a maximum diameter of each lower redistribution via from among the plurality of lower redistribution vias is in a range of 60 μm to 80 μm, and a maximum diameter of each of the plurality of upper redistribution vias is in a range of 10 μm to 30 μm.

12. The method of manufacturing the semiconductor package according to claim 1 , further comprising, forming a lower underfill resin between the base substrate and the interposer substrate, after disposing the interposer substrate on the base substrate.

13. The method of manufacturing the semiconductor package according to claim 1 , further comprising, forming an upper underfill resin between the interposer substrate and the at least one of semiconductor chips, after disposing the at least one of semiconductor chips on the interposer substrate.

14. The method of manufacturing the semiconductor package according to claim 1 , further comprising, disposing a heat dissipation structure on the base substrate, the heat dissipation structure covering the interposer substrate and the at least one of semiconductor chips.

15. The method of manufacturing the semiconductor package according to claim 1 , further comprising, forming barrier layers on the upper connection pads, respectively, after forming the upper redistribution structure.

16. The method of manufacturing the semiconductor package according to claim 15 , wherein the barrier layers are disposed between the upper connection pads and the upper connection bumps.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Eunseok
• Gu Minjeong
• Kim Joonsung
• Choi Jaehoon

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title