Wiring substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9455219-B2
Application number	US-201314141765-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Feb 13, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.

First claim

What is claimed is:

1. A wiring substrate, comprising:
a base wiring substrate including
a first wiring layer having a gold layer uppermost,
a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and
a second wiring layer formed under the first insulating layer and connected to the first wiring layer through a via conductor in the first via hole; and

a re-wiring portion including
a second insulating layer formed on the base wiring substrate, the second insulating layer in which a second via hole is formed on the first wiring layer, wherein the second insulating layer contact the first wiring layer and the first insulating layer of the base wiring substrate, the second insulating layer made of resin and
a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through a via conductor in the second via hole, wherein the re-wiring layer extends from an inside of the second via hole to an upper face of the second insulating layer, and a pattern edge of the re-wiring layer is arranged on the upper face of the second insulating layer,

wherein, the first via hole has a taper shape in which a diameter is set small gradually from the lower face of the first insulating layer toward the thickness direction thereof, and the second via hole has a taper shape reverse to the first via hole, and
the re-wiring layer is formed of a seed layer and a metal plating layer formed on the seed layer, the seed layer has a two layer structure in which a copper layer is formed on a titanium layer, and the titanium layer directly contacts the second insulating layer, and
a width of the seed layer is equal to or wider than a width of the metal plating layer.

2. The wiring substrate according to claim 1 , wherein
an upper face of the first wiring layer and an upper face of the first insulating layer in the base wiring substrate is arranged at the same height position, and
the second wiring layer protrudes from the lower face of the first insulating layer.

3. The wiring substrate according to claim 1 , wherein
a width of the re-wiring layer is set to be narrower than each width of the first wiring layer and second wiring layer, and
a thickness of the second insulating layer is thinner than a thickness of the first insulating layer.

4. The wiring substrate according to claim 1 , wherein a line:space of re-wiring layer is selected from a range of 1 μm:1 μm to 5 μm:5 μm.

5. The wiring substrate according to claim 1 , wherein the first wiring layer of the base wiring substrate has a three layer structure in which a copper layer, a nickel layer, and a gold layer are formed in order from a bottom.

Assignees

• Shinko Electric Ind Co

Inventors

• Shimizu Noriyoshi
• Kaneda Wataru
• Rokugawa Akio
• Koyama Toshinori

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/095

  of vias therein · CPC title